Tektronix Certus 2.0 eases debug of ASIC FPGA prototypes
Tektronix, Inc., has introduced version 2.0 of its Certus ASIC prototyping debug solution, building on capability the company acquired with their purchase of Veridae Systems in July, 2011. Certus integrates directly with RTL design flows, so that verification engineers can more easily incorporate embedded instruments to increase their visibility of ASIC prototype behavior.
Brad Quinton, Chief Architect for Certus, says that traditional debug methodologies require designers to guess where a bug might occur before compiling the FPGA prototype, which can require lengthy iterations of synthesis and place & route cycles whenever a new set of probes is required. Certus 2.0 enables designers to pre-instrument up to one hundred thousand signals per FPGA device, essentially eliminating the need to re-compile the FPGA when a new set of signals needs to be observed.
Quinton says that Certus requires only one Lookup Table (LUT) per signal, and one or two Block RAMs. He compares Certus to traditional debug tools, which he says can probe a maximum of only 1024 signals and require extensive LUT and memory resources. Certus takes advantage of the ability to infer observability of signals, in order to expand the number of signals that can be monitored beyond those that are directly probed. Tektronix has found that, for most circuits, there will be 3-5 inferable signals per direct observation.
Through proprietary signal compression techniques, Certus can monitor millions of trace cycles. In one example of monitoring Linux boot on an AMBA AHB bus, Certus was able to monitor a trace depth of 3.31M cycles, using two block RAMs, and providing a compression ratio of 2,873 X. The Certus software can also automatically identify and instrument RTL signals based on type and instance name, so that user can easily monitor all flip-flops, state machines, or interfaces, for example.
As ASIC designs continue to get larger and larger, verification engineers seek out the largest FPGAs available to avoid partitioning their prototype across multiple devices. Multi-FPGA prototypes are often still required, which can complicate the debug process, by requiring the stitching together of test patterns from multiple devices and clock domains. Certus addresses this issue by providing a time-correlated view of probe traces across partitions. Since Certus can instrument test probes after a design is partitioned, users are not required to do additional work to decide how test probes need to be partitioned as well. Tektronix says that Certus can provide a holistic view of an ASIC design across 2-10 FPGAs and 5-12 clock domains. Users can select a new set of signals to monitor by simply reconfiguring the Certus Infrastructure over the FPGA prototype board’s JTAG port, a process the company says takes just minutes.
The Certus 2.0 ASIC prototyping debug solution is available now and is priced at $19,500 U.S. MSRP for a one year term-based floating license.