Nick Heaton, Cadence

• Functional and performance verification of SoC interconnects

  Nick Heaton Cadence and Avi Behar Cadence

  Verifying interconnect Intellectual Property (IP) – the "glue" that holds together the cores and IP blocks in a System-on-Chip (SoC) – has become more complicated with advanced SoCs, which require special interconnect IP to perform the on-chip communication function. As a result, functional and performance verification of these SoC interconnects has taken on a new level of complexity. Tools have been developed to simplify verification while providing design engineers the ability to find and fix interconnect problems much earlier in the design cycle.