Advances in EDA design methodologies led by next-generation FPGAs
Advances in EDA design methodologies led by next-generation FPGAs
FPGAs have become some of the most important drivers for development of leading edge semiconductor technology. The complexity of programmable devices, and their integration of diverse high-performance functions, provides excellent vehicles for testing new processes. It’s no accident that Intel has selected Achronix and Tabula, both makers of programmable devices, as the only partners that have been granted access to their 22 nm 3D Tri-Gate (FinFET) process. In February, Intel also announced an agreement with Altera, which will enable the company to manufacture FPGAs using their next-generation 14 nm Tri-Gate process.
In parallel with driving manufacturing, FPGA technology development must also include enhancements to design tools and flows. As vendors strive to make their devices more SoC- and ASIC-like, they are also adopting standards and collaborating with EDA companies to integrate their tools more seamlessly. These collaborations are producing great benefits for designers, as FPGA design methodologies are leading the way in areas that the EDA industry has long been promising new capabilities, such as in Electronic System Level (ESL) synthesis, IP integration and re-use, and higher-level tools for software/hardware co-design.
FPGA design methodologies have long integrated EDA point tools, such as simulation and PCB design, into FPGA vendor’s design platforms. Now, vendors such as Synopsys, with their Synplicity tools, and Xilinx with Vivado, are collaborating to build more complete integrated top-to-bottom flows. To address the greater complexity of FPGAs that may now contain up to two million equivalent logic cells, Synopsys has added Hierarchical Project Management (HPM) to Synplicity. HPM supports distributed design teams and parallel development, enabling partitioning of RTL and sharing of design debug tasks. Xilinx has adopted the industry-standard Synopsys Design Constraint (SDC) timing constraints (to replace Xilinx proprietary UDC) in a design flow that can be driven from standard Verilog HDL.
Easing IP integration
Easier integration and re-use of semiconductor IP, especially when sourcing from multiple vendors, has been one of the greatest challenges to SoC designers and EDA tool flows. With the advent of higher capacity FPGA-based SoCs that utilize embedded ARM cores, those same challenges are now extended to the world of FPGA design.
One of the methods that the EDA and IP industry has developed to ease the problem is the adoption of a standard for IP description formats, the IP-XACT standard. IP-XACT was originally developed by the SPIRIT Consortium of companies that included ARM, Cadence, Mentor, and Synopsys. SPIRIT merged with EDA Standards organization Accellera in 2010. The IEEE adopted IP-XACT as the IEEE Std-1685 in 2009, and has made the specification available to download free from the organization’s website. The specification defines the use of XML meta-data to document the characteristics of IP, and an API to enable integration with EDA tools.
Xilinx has announced that they are supporting IP-XACT in their new Vivado IP Integrator (IPI), to ease the integration of their own and third-party IP. IPI is available to Xilinx’s early access customers along with the release of the latest revision of the Vivado Design Suite 2013.1. In a demonstration video from Xilinx, IPI appears to provide a very easy to use schematic-driven graphical user interface, which enables “correct-by-construction” block-level assembly of complex designs. Xilinx says the system can also be run in a tcl script-driven mode.
IPI enables users to select IP blocks from a library, place the blocks on a schematic, and then simply point and click to draw the interconnections between blocks, I/O pins, and AXI busses. The system prevents invalid connections from being made, and alerts the user to errors with a built-in validation function. A user can start by selecting the target FPGA from the Vivado library or choose one of Xilinx’s evaluation boards, which will include information on other onboard components such as external DRAM, so that interfaces can be included as part of the FPGA design process. Designer assistance is provided to ease construction of larger functional blocks, such as MicroBlaze processor subsystems. After completion of the block-level design, and final DRC validation, users can utilize Vivado’s HDL generation functions to create Verilog or VHDL to drive synthesis and place and route.
Industry standards enable higher levels of abstraction
Building on their 2011 acquisition of AutoESL, Xilinx also says that they have expanded their C/C++ system-level design library for High-Level Synthesis (HLS) in the new Vivado release. Xilinx is targeting the growing market for embedded vision applications, following on their participation as a founding member of the Embedded Vision Alliance, with support for industry standard floating point math.h operations and real-time video processing functions. Designers of embedded vision systems will be able to utilize Vivado HLS integrated with the Open Source Computer Vision Library provided by the OpenCV organization. OpenCV is an open source BSD-licensed library of computer vision functions, which supports Windows, Linux, Mac, Android and Apple iOS operating systems. Vivado users will be able to develop embedded vision applications for the dual-core ARM Cortex A9 processor system in Zynq FPGAs, augmented with special-purpose hardware accelerators built in the programmable logic fabric.
Today’s most advanced SoCs are highly parallel heterogeneous computing systems, which challenge the traditional low-level HDL-based programming model. Altera has been leading the FPGA industry in promoting the use of OpenCL, an industry standard for parallel programming of systems containing a mix of CPUs, GPUs, and DSPs, which is maintained by the Khronos Group. In November last year, Altera released their first SDK for OpenCL to early access customers, as part of the version 12.1 update of their Quartus II suite of design tools. Hardware platforms that support the OpenCL SDK are becoming available, starting with the Nallatech 385 PCIe accelerator card, which employs Altera Stratix V FPGAs.
The future of FPGAs
Advances in FPGA tools and flows are good news for designers of programmable logic systems as well as ASIC and SoC designers. At a recent Synopsys User Group tutorial on the Synplicity-Vivado flow, the large majority of attendees were involved in FPGA prototyping, where the latest high-capacity FPGAs have become critical tools for design validation and signoff for complex SoCs. By utilizing the same design languages and standards for both ASIC and FPGA design, much duplication of effort can be eliminated and faster time-to-market will result.