Approaches and tools for FPGA mixed-signal integration

Multiple methods for integrating ADCs into FPGAs are available, but the right implementation is contingent upon the signal being measured.

As FPGAs become more popular in the electronic design community, the approaches and tools used to integrate analog functions such as ADCs with these digital chips must be refined. Customer demand for high reliability, small footprint, and low power means that engineers have few choices and must look outside the box in their approach to mixed-signal integration with FPGAs.

FPGAs have exploded in popularity in recent years due to their relative low cost and high performance for digital signal processing tasks. The advantages of digital processing, reprogrammability, and variable cost structure have fueled this fast growth. Ironically, as the world has gone “digital,” demand for analog chips and components to grab continuous, real-world data has also risen quickly. As the breakeven unit decision between FPGA and ASIC continues to narrow, one large challenge continues to exist: For the FPGA market to continue growing, digital engineers need robust tools and effective solutions to integrate mixed-signal functions in their digital designs.

Three approaches generally exist for integrating Analog to Digital Converters (ADCs) with FPGAs: external off-the-shelf components, “mixed-signal” FPGAs, and digital ADC implementation. The traditional approach is to add off-the-shelf external ADC components. FPGA manufacturers responded to market demand for analog functionality by introducing “mixed-signal” FPGAs with ADCs in the packaged device. These mixed-signal FPGAs have significant advantages and a few drawbacks (really, when do we engineers ever get exactly what we want?). A third approach, which can fill in the gaps for many applications, is to use a digital ADC IP core to implement ADC functionality directly in the digital fabric of an FPGA. All three approaches are significantly different and require different flows and tools for effective integration.

The external components approach

The traditional integration of ADCs with FPGAs requires external parts. The process involves sourcing and selecting the proper component from an analog parts vendor and understanding how that component will affect size and power budgets. Tradeoffs exist between size, power, and performance. For many applications where size and power are not an issue, this approach works very well. Mixing and matching parts can be an easy way to meet cost budgets for projects that do not require strict optimization. Additionally, for very-low-volume applications, this may be the best approach as many simple ADCs are low cost. However, with the drive to low-power, portable, and high-reliability electronics in consumer, military, medical, and aerospace applications, there is room for improvement. In these markets any external connection point is a possible point of failure, so decreasing external part count would be very valuable. Lastly, for these same markets, system certification or recertification is an issue due to possible discontinuation of a part by a vendor. Certification requires significant resources to be achieved, and is easiest if done only once. In space exploration, this can be of particular concern.

Tools for external part verification

Verification at the PCB level can be divided into two arenas: small designs below 50 MHz operation and complex designs above 50 MHz. Smaller designs below 50 MHz can be verified using interface timing diagrams and a scope. The higher-speed designs require simulation tools such as HyperLynx[1] from Mentor Graphics, which is capable of board-level verification, signal integrity, and other features. Like all simulators, board-level simulators also require good models. Most ADC part vendors provide models with their semiconductor devices. However, when an FPGA design is involved it takes additional time and resources to generate the cycle equivalent model(s) for the FPGA to support PCB simulation. No matter the size, speed, or complexity of the PCB design, using a CAD tool like HyperLynx will verify and validate signal integrity and ensure faster design times.

The “mixed-signal” approach

FPGA vendors have done a good job of responding to the market’s need for ADC inte-gration. Xilinx and Microsemi have great approaches to covering the broad market. By placing one or two 500 KSps or 1 MSps ADCs in the package most applications are covered. These packages are more reliable than the external components approach, and have a smaller overall footprint. These mixed-signal FPGAs naturally command a price premium over other FPGA families for providing packaged ADC functionality. Depending on the product strategy and cost structure, the price premium may be well worth paying. For instance, if the product strategy is to constantly lead in terms of performance, it probably also commands a price premium, and the unit costs may not be that big of a deal. On the flip side, if it has a “continuous cost cutting” strategy, living with this approach may be required until needs can be met more adequately.

Customization is not much of an option in this approach. ADC resolution, sample speed, and number of channels are generally fixed by the vendor. This allows FPGA vendors to support a large swath of the market, but may come at the expense of the power budget. For example, running a voltage measurement at 1 MSps is like using a sledgehammer to drive the head of a pin. The extra speed will negatively impact the power budget. Complex designs these days can require upwards of 48 measurement channels. With mixed-signal FPGAs, adding external analog multiplexers or more mixed-signal FPGAs is the only solution to accommodate the number of channels.

Mixed-signal FPGA simulation and verification tools

Currently, FPGA tools for true mixed-signal simulations are not available. ModelSim[2], however, does support mixed languages such as Verilog, VHDL, and Verilog-A. Depending on the complexity of the analog portion of the design, ModelSim can be used to validate functionality at the mixed-RTL level. A mixed-signal simulator should be used to determine analog performance. However, to determine actual performance a true mixed-signal simulator should be used, such as Mentor ADMS[3] or Cadence AMS[4]. They will also require accurate SPICE models to determine performance, which might be difficult to obtain. Both methods take simulation time or functionality, and more simulation time to determine actual performance.

Digital implementation approach

Some “analog” functions can also be im-plemented using only the digital fabric of an FPGA or ASIC. A crude scheme can be worked up by using an LVDS and small set of resistors and capacitors (Figure 1). Several white papers from Xilinx, Lattice, and others exist on the topic. These papers show resolutions of only 8-9 bits while requiring very high clocks to achieve that performance. Additionally, error rates have been shown upwards of 15 percent.

Figure 1: Some analog functions can be implemented using an FPGA or ASIC digital fabric, shown here using an LVDS and a small set of resistors and capacitors.

External ADCs are unnecessary because a digital ADC is embedded in the FPGA fabric. The removal of external parts lowers board space, and the digital architecture and slower clocks lower power consumption over a comparable analog ADC. Testing is made easy by using the digital test methodology available from any FPGA vendor. These cores can be made rad hard/tolerant by using a rad-hard-tolerant FPGA.

Despite these many advantages, the generic digital ADC technique is severely limited in resolution and bandwidth. This approach will generally not work for applications requiring MHz bandwidths, such as RF communication, as those bandwidths are much more difficult to achieve with digital resources. Here, the external parts approach and perhaps the mixed-signal FPGA approach hold the advantage for those applications.

Through proprietary signal processing, Stellamar can achieve digital ADC performance upwards of 14-bit resolutions and 100 kHz bandwidth with error rates of less than 1 percent and no temperature drift. This method works for applications spanning DC measurements, temperature, touch, acceleration, motor control, audio, and some optical networking tasks. Stellamar works with Xilinx and Microsemi to provide Digital ADC IP cores to engineering teams that require a customized combination of low power, small size, and high reliability, and currently works with aerospace companies on satellite builds and with consumer electronics companies looking to reduce part count to lower cost and increase reliability.

Tools for digital simulation

Current FPGA tools are quite adequate to perform all digital simulation with an embedded digital ADC. This provides a level of certainty at the RTL and gate levels to the entire design before configuring an FPGA. This verification and validation is achieved by using any Verilog simulator supplied with the standard FPGA toolkit, which is ModelSim in most cases. Since a digital ADC is described in Verilog or VHDL, any FPGA can be targeted without the need for additional models other than the supplied FPGA digital library. With the added flexibility of reprogramming and the availability of different-sized FPGAs, designers can optimize not only the system by defining the exact ADC requirements, but also the power and board. A typical FPGA design flow starts with the instantiation of the digital ADC IP into the design. Then the entire design is synthesized to the FGPA gates using the tool provided with the FPGA toolkit. Post-place and route gate level timing simulation is usually performed with the provided ModelSim simulator to perform an all-digital simulation. This validates the gate level implementation of a mixed-signal design without the need of a mixed-signal simulator.

Reintegrating analog and digital

The growth of the FPGA market for high-reliability and low-power applications hinges on better integration of “analog” with “digital.” Three approaches for implementing ADCs with FPGAs are available. External components can be easy to use but occupy more board space. Mixed-signal FPGAs are easily accessible and offer great performance, but are technology-dependent, more expensive than standard FPGAs, and are limited in array size. Embedded Digital ADC cores are technology-independent and offer a migration path to ASICs, use digital testing, and are optimized for size and power; their main drawback is a limitation on bandwidth.

From a system perspective, the mixed-signal FPGAs and embedded Digital ADCs are best for systems that require certification, such as medical, consumer, and military devices, as they remove the possibility of a system change due to end-of-life of an external ADC.

Good mixed signal integration starts with understanding what signals are being measured and what is required to measure those signals. Once requirements are accurately established, an approach can be selected. No matter which method is used, a PCB simulation should be run at the board level in all cases. The ability to use a Digital ADC core can simplify the design integration and validation of an FPGA-based mixed-signal design.

Each approach and tool set have real value to the engineering team, but each have their drawbacks. Looking to the future, more analog functions such as power management and clocking will be able to take advantage of digital tool sets for modeling and testing.


  1. Mentor Graphics HyperLynx:
  2. ModelSim:
  3. Mentor Graphics Mentor ADMS:
  4. Cadence AMS:

Allan Chin is CEO at Stellamar and has more than 30 years of design experience with high-performance digital and mixed-signal systems. His broad expertise covers many areas of IC design, including system requirement definition, chip development, mixed-signal simulation, verification, prototyping, and lab testing. Allan has a B.S. in Electrical Engineering from Marquette University, Milwaukee, Wis., and holds nine patents. Allan can be reached at