Big 3 Executive Interview - Lip-Bu Tan, CEO, Cadence Design Systems

Lip-Bu Tan is President and Chief Executive Officer of Cadence Design Systems, Inc., and has been a member of the Cadence Board of Directors since 2004. He also serves as Chairman of Walden International, a venture capital firm he founded in 1987.

Tan received an M.S. in Nuclear Engineering from the Massachusetts Institute of Technology, an MBA from the University of San Francisco, and a B.S. from Nanyang University in Singapore. He serves on the Board of Directors of both the Electronic Design Automation Consortium (EDAC) and the Global Semiconductor Association (GSA).

University research remains an important contributor to the advancement of design automation technology. New algorithms or models are still important, though in many cases collaboration and information sharing are required in order to implement new technology. For example, Cadence is working with Professor Chenming Hu and his group at the University of California, Berkeley to develop simulation models for FinFETs, which Dr. Hu invented. A complete solution will require not only the definition of a simulation model, but also the characteristics of specific devices in specific manufacturing processes – information that must be shared by the fab or foundry.

Also, participation of university students at industry conferences remains strong, and Cadence has well-attended academic programs at our CDNLive conferences, where university students present papers and compete for awards.

EDA| Cadence Design Systems, Mentor Graphics, and Synopsys, the three largest EDA companies, were all founded nearly 25 or more years ago. What do you think has been EDA’s biggest innovation in that time?

It’s hard to pick a single development that is the biggest innovation for all different kinds of design, but in general the big innovations involve abstraction, automation, and reuse. It’s the power of abstraction that has raised EDA from drawing simple geometric shapes for individual transistors to synthesizing billion-transistor ICs from text descriptions in a programming language like SystemVerilog or C. The ability to automatically assemble blocks into complete, optimized designs kept development schedules from exploding along with the size and complexity of chips. And design reuse is now evolving from a craft to an industry, as it must in order to meet the needs of expanding SoC designs. In the end, both automation and design reuse rely on abstraction, so if we must narrow the answer to one characteristic, then abstraction – in all its forms – has been the cornerstone innovation of EDA.

EDA| How does Cadence Design Systems continue to foster innovation?

In our industry, innovation is not optional. EDA is driven by the rising complexity of new designs and the growing challenges of new semiconductor technology. At Cadence, we are engaged in a series of deep collaborative projects with leading ecosystem partners and key customers. The goal is to anticipate issues and create solutions that will enable design of the next generation of SoCs and end products. Often, our teams are literally working side-by-side in shared offices, so our engineers have direct exposure to issues that inspire innovation. Cadence also sponsors a worldwide series of customer conferences called CDNLive, which brings technology users and industry experts into contact with Cadence engineers to discuss new techniques for realizing advanced silicon, SoCs, and systems.

EDA|We have been hearing more about 3D ICs in the last few years. Do you think that true, stacked die, 3D ICs will require a change in design paradigm to create growth for EDA, or will most of the needs be fulfilled by existing 2D design tools?

Designing 3D ICs will require changes not only to design tools, but also to methodologies, IP, and, to some degree, how the semiconductor industry works. The EDA flows for 3D ICs will be built on top of proven flows for 2D, but will add a layer of essential new technology to manage issues like the signal integrity, power, and thermal effects of 3D construction. Cadence has developed leading technology for 3D IC design and verification over the past few years, and our recent acquisition of Sigrity further strengthened that portfolio by adding analysis tools that are essential for developing high-performance chips.

EDA|What is the biggest challenge facing the EDA industry today?

There are so many different things that affect the success of a new IC or product that the biggest overall challenge is the interdependency of all of those factors. For example, process technology and circuit design interact to affect power consumption; both of those also interact with layout to affect hardware performance. Also, hardware design interacts with embedded software to determine the overall characteristics of a device – like features, usability, and application support. As each factor is becoming individually more complex, the overall challenge is increasing rapidly. Technology development can help address complexity, but a crucial part of the solution is for ecosystem partners to manage the scope of interdependencies through collaboration. Instead of each partner spending time and money to develop a universal solution to support all possible permutations of other factors, companies collaborate to define and optimize solutions to manage the interdependencies of the most important scenarios. Most of the really big successes in the semiconductor industry today are the result of collaboration between software providers, IP and EDA companies, application creators, IC foundries, and others.

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