Boosting embedded DSP processing with open-source-based HPEC supercomputer performance

Radar, SIGINT/EW, Imaging, and other ISR applications are among the most compute-intensive defense and aerospace applications. The amount of data coming into air and ground platforms from a steadily increasing number and type of sensors is driving the need for embedded processing at the supercomputing level. Great strides are being made thanks to recent developments in the effort to bring commercial High-Performance Computing (HPC) technologies into the SWaP-constrained Mil/COTS environment, advances in open-standard system architectures that can support the newest generations of multicore commercial processor chips, and the highest bandwidth serial fabrics.

Open source opens up high-performance possibilities

Recently, Curtiss-Wright Controls Defense Solutions (CWCDS) undertook two demonstrations that presented breakthroughs in these efforts. In December 2011, a demonstration was conducted that successfully showed OpenFabrics Enterprise Distribution (OFED) software running on a dual 2nd generation Intel Core i7 DSP module enabled with Gen2 Serial RapidIO (SRIO). The resulting performance showed, to the company’s knowledge, the industry’s highest performing High-Performance Embedded Computing (HPEC) system on a FLOPS per watt basis.

OFED is an open source software component that abstracts fabrics and operating system Remote Direct Memory Access (RDMA) from higher level software. OFED is governed by the OpenFabrics Alliance, which has many contributors across the industry. OFED supports multiple fabrics such as Serial RapidIO, Ethernet, InfiniBand, and multiple OSs including Linux and Windows. The use of open source APIs enabled abstraction of heterogeneous software and effectively showed commercial HPC architectures running on a rugged, embedded defense and aerospace subsystem.

The demonstration included OpenMPI, an open source implementation of the Message Passing Interface (MPI); RapidIO RIONet, an open source component that transports Ethernet frames seamlessly over RapidIO messages; and DAPL/UDAPL InfiniBand fabric APIs. OFED support enables system integrators to run their application software coded for Ethernet and InfiniBand systems natively on CWCDS rugged, deployable hardware that transparently runs the Gen2 Serial RapidIO fabric.

The HPEC system demonstrated supports over 3.7 Intel AVX TFLOPS and 224 GBps of fabric connectivity in a standard 16-slot OpenVPX chassis. The HPEC system supports eight Intel cores and bandwidth rates of 8 GBps to the data plane. The demonstration utilized COTS silicon and open source software to further emphasize the HPEC system’s open architecture compared to alternative OpenVPX systems that require proprietary RapidIO IP and software stacks. The open architecture approach fosters competition, eliminates vendor “lock-in,” and reduces costs through competition.

Fast Serial RapidIO data

Also in March 2012, the company showed the first known demonstration of an HPEC 6U VPX subsystem with Intel, Freescale, Xilinx, and IDT Interoperability running on Serial RapidIO. The heterogeneous OpenVPX-based HPEC system used in this demonstration delivered extremely high data transfer efficiency. Serial RapidIO (SRIO) data was transmitted between an Intel 2nd Generation Core i7 processor, Freescale 8640 Power Architecture processor and a Xilinx Virtex-6 FPGA, which constitute the three leading building blocks of high-performance DSP embedded systems for defense and aerospace C4ISR applications such as image, signal, and radar processing. The demonstration was based on the company’s rugged COTS OpenVPX board modules, and was also the first known demonstration to show an Intel CPU running Gen 2 SRIO, an achievement made possible through use of the IDT’s groundbreaking Tsi721 PCIe2-to-SRIO2 RapidIO bridge.

Results of the demonstration include data transfers between Intel CPUs rated at 1.7 GBps, achieving 95 percent of the theoretical maximum wire speed for a given physical link into the switch fabric (excluding overhead). Furthermore, these results were achieved with a near-zero overhead burden on the processor thanks to the high-speed DMA feature of the Tsi721 and SRIO’s inherent guaranteed-by-hardware data transmission. The outcome showed that offloading the host processor results in improved overall system performance.

A “super” future for military systems

The emergence of COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained embedded military applications. The result will be more real-time, actionable intelligence to help the warfighter successfully and safely accomplish their mission. As sensor data continues to proliferate, the greater processing capability of HPEC systems will help enable system designers to fully capture, analyze, and exploit the ever-increasing amount of raw data. For more information on these HPEC technology demonstrations, please contact Rob at