Can your PCB handle the speed?

8The JESD204B high-speed data converter I/O standard provides for serial interface bit rates of up to 12.5 Gbps. Many system designers are embracing this “upgrade” to the digital interface. Its faster serial interface allows them to use fewer high-speed serial transceivers on their FPGA or ASIC. This reduction in the number of I/O traces enables smaller packages, smaller PCBs, and smaller overall product form factors. However, designing a reliable physical interconnect for data rates exceeding 5 Gbps may involve additional effort. As the speed increases, the transmission distance needs to be accounted for and additional channel modeling may be necessary, possibly involving a 3D field solver to ensure signal integrity.

Modern high-speed converters mostly employ a voltage mode logic (VML) or a current mode logic (CML) serializer/deserializer (SerDes) transmitter. In a CML transmitter, the two switching transistors are used to steer a constant current through the termination resistor, causing a differential voltage drop at the receiver (Figure 1).

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Figure 1: Illustration of a CML transmitter.
(Click graphic to zoom by 1.9x)

A voltage mode transmitter generates the output voltage via a pair of unity gain followers onto the load impedance. Since there is no internal 50 Ohm pull up resistor the VML driver is a lot more power-efficient than a CML driver.

As next generation high-speed data converters are moving into more advanced, lower geometry CMOS processes in order to further increase the sampling rates, the inherently faster transistors also enable a design of a fast and very power efficient serial transmitter and receiver. For example, the ADC16DX370 can transmit the sampled data of one channel over just one single lane at 7.4 Gbps, consuming only about 83 mW. The serial transmitter of the ADC12J4000 only consumes about 50 mW per lane at 10 Gbps.

Eye diagram

The quality of the serial link is usually measured by generating an “eye diagram” on a given PCB transmission channel (Figure 2). The eye diagram is generated by overlaying many data bits using a fast oscilloscope triggered on a reference clock. The eye diagram essentially gives guidance on the ability of the receiver to recover the correct logic level of the incoming .

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Figure 2: Eye diagram of a serial link.
(Click graphic to zoom by 1.9x)

In the eye diagram, the vertical opening shows how much attenuation is present in the transmission channel. A larger opening significantly increases the ability of the receiver to determine the proper logic level of the sampled bit. On the horizontal axis the eye opening is reduced by the jitter. Jitter specifies the deviation from the ideal switching point when the signal crosses through 0 V (zero crossing point). A smaller jitter number translates to more timing margin.

The receiver then tries to determine the logic level of the current, incoming sample as close to the center of the bit period as possible in order to maximize the amplitude and jitter margin.

As the jitter has such a big impact on the link quality, the JESD204B standard specifies the jitter requirements for both transmitter (TX) and the receiver (RX). The transmitter jitter is measured directly at the output. It documents how much the transmitter itself degrades the eye diagram prior to going into the transmission channel.

The receive jitter is a measure of the jitter tolerance requirement. It indicates how much jitter the receiver has to tolerate while still extracting the correct information from the incoming data stream. The TX and RX jitter requirements are specified for three different data rate range (up to 3.125 Gbps, up to 6.25 Gbps, and up to 12.5 Gbps) as illustrated in Figure 3. The requirements get progressively tougher as data rates increase, primarily because higher frequencies also experience a larger amount of loss on the transmission media.

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Figure 3: Jitter requirement comparison-based on maximum link data rate.
(Click graphic to zoom by 1.9x)

PCB design considerations

As the serial data rates increase beyond 3 Gbps, the physical PCB design needs to get a lot more attenuation than in the past. When using parallel LVDS with a max data rate of ~1 Gbps, for example, the primary PCB design challenge was in matching the lengths of the traces across the LVDS bus. For multi-gigabit transceivers, the PCB (or channel link if connectors and so on are used) attenuation versus frequency is the highest priority. It determines if the longer traces equate to more signal amplitude loss and increased jitter at the 0 crossing.

In order to examine the channel loss a little closer, the system designer first has to look at what frequency range the serial link will operate. The worst case fundamental frequency of the serial output data stream is when the maximum bit transitions occur, so in essence when transmitting a 1010 pattern, which is possible in the 8b/10b encoding. So the maximum fundamental frequency is half the data rate. The third and fifth harmonic of that fundamental frequency is what creates the fast slew rate when trying to transmit a square wave.

Attenuation of the higher order harmonics directly translates to longer rise and fall times which in turn increase the jitter at the zero crossing point. So a higher channel loss reduces the eye opening both vertically due to more amplitude attenuation and horizontally due to increased jitter. Figure 4 illustrates how the attenuation increases proportionally with the length of the interconnect for a given PCB material (FR4 material with 6 mil traces).

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Figure 4: Comparison of amplitude attenuation versus trace length for a given FR4 PCB material.
(Click graphic to zoom by 1.9x)

System designers have a few different options available to them to compensate for a smaller eye opening:

  • Higher quality PCB materials than standard FR4 can be used which have less loss across frequency. Most PCB manufacturers today allow using the expensive material only on layers with the high-speed traces in order to minimize additional cost.
  • Modern data converters provide quite a lot of flexibility in configuring the JESD204B link. For example, the DAC38J82 can be configured to use one lane per at 12.5 Gbps, or two lanes at 6.25 Gbps for the maximum sampling rate. This allows the tradeoff of board area and number of lanes against the length and speed of the interconnect.
  • PCB designers can use more advanced simulation tools like a 3D field solver or IBIS AMI models. These advanced tools help to minimize trace impedance discontinuities and to design vias that closely match 50 Ohms.
  • Employ de-emphasis or pre-emphasis in the SerDes transmitter as well as active equalization in the SerDes receiver

Equalization techniques

As previously illustrated, the lossy PCB material can be represented as a lowpass filter in the frequency domain. In order to counter/equalize the high frequency attenuation (insertion loss), a frequency response can be added to the transmission chain as pre- or de-emphasis in the serial transmitter and/or as active/passive equalization in the serial link receiver (Figure 5).

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Figure 5: Equalization of a lossy transmission channel.
(Click graphic to zoom by 1.9x)

Pre-emphasis adds extra output current to improve the signal rise and fall times, which basically boosts the amplitude of the higher order harmonics. On the other hand, de-emphasis decreases the signal amplitude when no bit transitions happen (essentially attenuating lower frequency range).

Hence, pre-emphasis and de-emphasis have about the same effect when trying to compensate the channel insertion loss. The ideal outcome is a transmission channel with a flat frequency response.

The ADC16DX370 employs a low power VML driver with several different options for de-emphasis and output amplitude levels which can be tuned to closely match different channel loss profiles as shown in Figure 5.

The SerDes receiver in the DAC38J84 provides full adaptive equalization, which automatically compensates the channel insertion loss by adjusting the placement of a transfer function zero based on the received data and thereby minimizing inter-symbol interference. Additionally, its receiver includes built-in eye scan and equalization analysis functions to determine if the transmit partner is applying more or less equalization than necessary.

The value of de-emphasis and pre-emphasis becomes quite apparent when examining the eye diagram at the receiver with and without de-emphasis as illustrated in Figure 6.

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Figure 6: Eye Diagram after 20 inches of FR4 using ADC16DX370 at 7.4 Gbps.
(Click graphic to zoom by 1.9x)

Less crowded PCB design

High-speed data converters with JESD204B enable a cleaner and less crowded PCB design by replacing the traditional parallel digital interface with fast serial interconnects supporting data rates up to 12.5 Gbps. Although board layout may become a little more challenging, recent state-of-the-art data converters like the ADC16DX370 and the DAC38J84 provide very flexible equalization circuits to ensure a robust and reliable communications link despite the fast data rate.

Thomas Neu is a Systems Engineer for TI’s high-speed data converters group where he provides applications support. Thomas received his MSEE from Johns Hopkins University, Baltimore, Maryland. He can be reached at ti_thomasneu@list.ti.com.

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