Design techniques for FPGA power optimization
A variety of factors – from the micro to the macro, from conserving battery life to lessening global warming – has pushed power conservation rapidly up the list of system designers’ concerns. Engineers have ranked power consumption first in recent surveys on key design priorities or as a close second next to performance, density, and cost.
FPGAs present unique challenges when it comes to power consumption. Armed with a good understanding of these challenges and new technology, techniques, and tools to meet them, system designers can realize the advantages of an FPGA-based portable system deployment. This is increasingly crucial as FPGAs are depended on more and more to provide flexibility and fast time to market in an expanding universe of applications.
Assessing a given FPGA architecture’s suitability for power-sensitive applications today warrants an in-depth examination of the power equation. We can do this by examining FPGA power characteristics and their effects before diving into optimization tools and possible design solutions, which include, among others, partitioning, clock and power gating, and voltage scaling.
Empowering low-power design
Depending upon the type of FPGA technology chosen, many different factors make up power consumption: static, dynamic, power-up (or inrush), configuration, and various low-power modes.
Static and dynamic power are familiar concerns for all IC designers. Leakage current in several forms dominates static power: sub threshold leakage, junction leakage, gate-induced drain leakage, and gate leakage. Dynamic power refers to power consumed during device operation and correlates with such factors as used functional resources (logic blocks, clock trees, embedded RAM, PLLs, and the like), loads and resistive terminations on I/Os, clock frequencies, data patterns and their arrival dynamics, signal activity or toggle rates, and signal static probabilities.
Designers considering volatile, SRAM-based FPGA solutions must also consider three other components of power. Inrush power and configuration power consumed during system and device functional power-up can be significant, as can the power required during sleep (static) mode. Also, since SRAM-based FPGAs are volatile, they must be booted up with an external device program typically held in a PROM, which adds both power and start-up delay to the system.
Despite the efforts of SRAM-based FPGA vendors to reduce power, these higher power components remain in the market, significantly increasing the overall system power consumption, especially when several FPGAs populate a single board or use power from a common supply on different boards. The impact is greater for systems with frequent on/off cycles. which must be considered when estimating battery life. Thus, when sizing power supplies or selecting batteries for SRAM-based programmable devices, system designers must account for configuration and inrush power dissipation. True flash FPGAs are nonvolatile, do not exhibit inrush or configuration currents, and have lower overall static power, thus making the design task easier and significantly lowering power. (Figure 1).
Another measure to remedy transistor leakage is to create cells with two levels of threshold voltage (VT). With this so-called multi-VT technique FPGA makers seek to reduce overall design leakage by deploying a minimum of low VT devices, which are more leaky, while maximizing the use of less leaky high VT cells. Multi-VT has been employed in the past in ASIC and ASSP offerings and is now being adopted by FPGA vendors.
In the IC design world, minimizing die size is a constant concern, for cost and numerous other reasons. Power can now be added to that list. The smaller the die, the smaller the static power consumption. Choosing the smallest possible die that meets the functional and other demands of the application will make it easier to meet power consumption objectives.
It is also important to choose an FPGA that makes it possible to optimize the use of resources such as RAMs, PLLs, and I/O technologies. FPGA architecture selection should include consideration of any low-power FPGA modes and other power-saving capabilities of dynamic resources such as PLLs, RC oscillators, and I/O banks. For example, given that lower reference voltages save power over the life of a system, choosing an I/O offering that supports both 1.2 V LVCMOS and/or 1.5 V LVCMOS standards makes it possible to utilize higher voltage I/Os if necessary.
Watch the clock
The dynamic power consumed by an FPGA is due largely to the charging and discharging activities of capacitive elements, such as logic resources and the interconnecting fabric (Figure 2).
By considering each of the functions in the dynamic power equation, you can lower power consumption. In the clock domain, for instance, you can decide which parts of the design need a fast clock or a slower clock. Switching speed is one component of the dynamic power equation. Logic that is being driven by a fast clock will be switching more frequently than logic that’s being driven by a slow clock. The designer knows which portions of the logic require a fast clock and which can be run at a slower speed and can therefore partition clocks according to the functions they control, conserving power.
Dynamic power can also vary widely as a function of placement and routing. For example, as two connected functional instances are placed closer together, the length of the route between the instances may be shortened, which in turn can reduce the capacitive loading of the net and lead to a reduction in power. Today’s FPGA development software typically can support Power Driven Layout to automatically accomplish this. Depending on the number of clocks and nets in the design, 25 percent or more overall dynamic power reduction can be obtained.
At the architectural level, it’s beneficial to examine the clocking scheme of the design to seek out ways to employ clock gating for the clock tree. If a design is powered up but not clocking a portion of the system, you can reduce dynamic power by not connecting the clock tree to that portion of the design. For example, if a clock serves one function that is needed and another that isn’t, a logic signal can be implemented to selectively control what functions are clocked and when, depending on the state of a control variable. Employing logic for clock gating may introduce clock skew however, which must be managed.
Another means of achieving power savings is to utilize any power-saving modes that might be available within the FPGA architecture. Supported modes typically are Active, Standby, or Sleep. In the active mode, the FPGA will be performing its intended function, but, depending on the application, when it doesn’t need to do anything, it could be put into a standby or sleep mode where power can be saved. Some FPGAs offer the ability to toggle into an ultra-low-power-saving mode in which the clock serving idle circuitry is turned off while device states are preserved. In this mode dynamic power consumption is eliminated because the clocks are off and static power is negligible. This technology has been available in ASIC devices and has recently emerged in FPGAs. Actel’s Flash*Freeze is an example of this ultra-low-power mode. The Flash*Freeze mode can be entered or exited in less than 1 microsecond and consumes less than 2 microwatts when in effect. A cell phone is a typical example of a system that takes advantage of multiple power saving modes by being active only when used and otherwise being in standby to conserve battery life.
Other power-saving design techniques
Selective power-down simply refers to shutting the power down to certain portions of a chip, or to certain chips on a board. Implement a multisupply strategy in which the power grid of some blocks is decorrelated from others in order to allow for selective shut-down. Power-down or sleep modes within the FPGA architecture can also be deployed to selectively power down blocks when not in use.
Macro optimization can also yield power savings. Some logic elements are offered in multiple versions optimized for high performance, high density, or low power. High-performance macros tend to consume more power than other versions, so power can be saved by deploying high-performance macros only when they are required. For example, a fast adder consumes more power than a slower ripple adder. Examination of the differences between them might reveal that the ripple carry adder consumes about one-tenth of the dynamic power compared to the fast adder. Depending on the speed required for a design and targeted functions, the low-power option might be perfectly adequate. This applies for almost any type of macro, including multipliers, FIFOs, and RAMs.
Time multiplexing and minimum I/O count design partitioning are techniques that can help switch an I/O bank on or off. Minimizing the different types of I/O technologies, ensuring that the right I/O technology is used, and reducing the I/O drive strengths and slew rates are also helpful.
Dynamic voltage scaling is another power-saving design technique. Power scales proportionally with the square of voltage, so reducing supply voltage can significantly impact power efficiency. If system requirements demand more performance than low-voltage I/Os can deliver, utilizing low-voltage I/Os on non-performance-critical pins and higher voltage I/Os for critical signals offers an excellent alternative. Some low-power FPGAs on the market today fully operate from a single 1.2 volt supply for the core and I/Os.
Power-aware design tools
A number of power-oriented FPGA design tools have emerged to help designers achieve more energy-efficient products within shrinking design cycles. Two such EDA capabilities are power-driven layout and power analysis.
Power-driven layout can be used to help minimize dynamic power. Power-driven layout tools examine interconnect between functional instances and target those nets having large activity-capacitance products (ƒ · C) for optimization. These tools also scrutinize the number of row and spine resources for clock nets, as those nets are typically among the largest and most active.
Typically, a post layout simulation derived Value Change Dump (VCD) file, used as a source file to drive the power driven layout, more accurately analyzes power than is possible by using a default general power estimation. The VCD file reports the actual net by net switching activity within the design. To accomplish this, you would first layout the design in a timing driven mode, back annotate, run simulation to generate the VCD file, import the VCD file into the project, and rerun layout in the power-driven mode (Figure 3).
Power-analysis tools can be used to examine the hierarchy of the design from a power perspective and further optimize power. Such tools examine each subcomponent in a design hierarchy and highlight power consumption, typically by instance, rank-ordered with the highest-consuming instances at the top. Careful examination of this information and subsequent manipulation of the design can result in significant power savings. At the top level or within the selected instances, respective power is noted by nets, gates, memories, I/Os, clock domains, or power supply rail. This approach pinpoints the power hotspots, so the designer can reduce the power.
As noted earlier, designs can operate in a combination of modes. Some power-analysis tools can report the average power consumption based on a power profile where the designer specifies the amount of time the design will operate. For example the designer could specify x percent time in active mode, y percent time in standby mode, and z percent time in Flash*Freeze mode. The analysis tool will report the weighted average power for the combination. This capability is helpful for picking a proper battery for the application, as battery life is significantly reduced when operating frequently in power-saving modes.
Lastly, in some tools, the simulation based VCD file can be used to report and display peak power by clock cycle or increment in time. This feature allows you to understand exactly what moment in time or which clock cycles experience high power, presenting another avenue for addressing and potentially reducing power in the design. (Figure 4)
Power is a critical concern for designers of FPGA-based systems, especially portable applications. Leading FPGA companies are introducing power-friendly FPGA architectures. EDA tools are stepping up with more sophisticated architectural and power-analysis tools to help users estimate the power consumption at different stages of the design cycle, as well as providing power-aware synthesis and layout capabilities.
Designing for low power starts with informed FPGA technology and device selection. Good design practices, such as controlling clock networks with gated clocks, exploiting the power-saving capabilities of the FPGA, and floor planning the design, lay the framework for a power-conscious design. Power-aware design tools aid these design practices by optimizing layout and automating the power analysis to identify in great detail the power consumption hotspots in the design, enabling designers to take corrective action. Armed with these strategies, techniques, and tools, the FPGA designer can reduce power and ultimately play an important role in larger energy issues from battery conservation to energy independence.
Fred Wickersham, Product Marketing Manager, Software Tools, at Actel has more than 25 years of experience in semiconductor marketing and product management. Prior to joining Actel in 2002, he held various positions in companies such as National Semiconductor, Philips Semiconductor, and LSI Logic. Wickersham studied at the Oregon Institute of Technology, and holds a Bachelor’s of Science in Business Administration from the University of Phoenix.