Developers throttle the bottleneck to grab maximum I/O bandwidth using FMCs

15Rob describes how FMCs have changed such tasks as analog signal detection and processing.

Recent months have seen momentum growing in the defense and aerospace market for the new FPGA Mezzanine Card (FMC) standard. FMC (ANSI/VITA 57) modules support the multi-GHz signal acquisition rates required to fully exploit the processing performance and I/O bandwidth delivered by the newest generation of FPGA devices used in demanding military applications such as Electronic Counter Measures (ECM), where high-bandwidth data input, high-performance processing, and minimum latency data output are critical. New products based on the standard, including FMC modules and host cards with multiple FMC sites, are entering the market.

An example of an application where FMCs provide an ideal fit is a subsystem that must do analog signal detection and processing, and then report the results to other parts of the system. The newest ADC devices sample in the GHz range with 8-bits of resolution, which can result in data streams of up to 3 GBps and generate many applications needing multiple channels. Today, with two FMC mezzanine cards, a 6U VPX baseboard with two large FPGAs, and an onboard processor, this application can be accomplished in a single slot. Previously this task would have required at least two to three times that volume. A VPX SBC with dual FMC sites can easily handle four of the 3 GBps ADC streams coming into the large onboard FPGAs, which can then perform filtering and detection as needed by the application. The processor coordinates these activities and can perform further processing before sending the data off to another part of the system such as a display. The FMCs make it possible to get the dense number of high-sampling ADCs into the FPGAs, thereby leveraging the boards resources and lowering the subsystem’s Size Weight and Power (SWaP) budget.

Prior to the debut of FMCs, a common approach for adding high-speed I/O to embedded COTS boards was to use PMC or XMC mezzanine cards. While this modular approach can provide good functionality, the full potential of the FPGAs to process data can be lost in data bottlenecks – especially as today’s high-end digitizer outputs have grown beyond the data transfer capabilities of PCI or PCI Express mezzanines. To mitigate these bottlenecks and take full advantage of FPGA high-speed I/O potential, the system designer’s best options had been to either directly incorporate the I/O into the FPGA board design, eliminating any flexibility to exchange or upgrade I/O technology, or to use custom mezzanine I/O modules, also eliminating flexibility because these bespoke modules are vendor-specific.

Desired bandwidth with freedom to alter I/O functionality

By using an FMC rather than a vendor-specific mezzanine I/O module, designers can maximize I/O bandwidth without giving up the flexibility to change I/O functionality. FMC modules are simple. They only carry I/O devices, such as ADCs, DACs, or transceivers. Rather than incorporating onboard processors or bus interfaces, such as PCI-X, FMC modules use the FPGA’s intrinsic I/O capability to separate the module’s physical I/O functionality from the FPGA board design of the module’s host, while maintaining direct connectivity between the FPGA and the I/O interface.

A key advantage of FMCs is that they can support significantly more FPGA-based processing resources on a carrier card, enabling a greater amount of processing to be done, reducing the need for data reduction or decimation. In comparison, PMC and XMC mezzanine cards are limited by their use of the PCI and PCI Express buses respectively and are often confronted with bandwidth that exceeds their capacity. In such cases the data must first be reduced within the FPGA.

Another aspect of FMCs worth highlighting is their ability to improve the system’s thermal dissipation. The latest FPGAs have large packages, some measuring up to 42.5 x 42.5 mm. Besides using a large amount of board real estate, these devices also have significant power budgets, and hence generate a lot of heat. For conduction-cooled systems, dealing with this additional heat is especially problematic. Placing the FPGAs on a mezzanine card such as an XMC means that they cannot conduct heat directly to the side rail of the card, thereby limiting their use in deployed systems. However, with the use of FMC, we can take advantage of these larger devices by placing them on the baseboard closer to the card edge, which can result in significantly improved thermal performance.

For rugged applications, FMCs can be air- or conduction-cooled. They can be used on many modular board-level standards such as VME, CompactPCI, AdvancedTCA, or VPX. And like the earlier PMC and XMC cards, FMCs can have I/O signals routed via a front panel bezel or through the base card and backplane for enhanced maintainability.

Similar in width, but only about half the length of a PMC card, the single-width FMC module measures 69 x 76.5 mm and provides a single connector to a carrier. The double-width version of FMC measures 139 x 76.5 mm and can support two connectors. VITA 57 defines two different connector options, a Low Pin Count (LPC) connector with 160 pins and a High Pin Count (HPC) connector with 400 pins. The connector is designed to support single-ended and differential signaling up to 2 Gbps and signaling to an FPGA's Multi-Gigabit Transceivers (MGTs) at up to 10 Gbps. The LPC connector provides 68 single-ended user-defined signals (or 34 differential pairs). The HPC provides 160 single-ended user-defined signals (or 80 differential pairs).

The FMC module’s MGT interfaces are able to support multi-gigabit serial links. Moving the copper or fiber-optic transceivers from the base FPGA design onto an FMC mezzanine module makes it much easier for a single FPGA host card design to support various physical interfaces. Furthermore, next-generation ADC and DAC chips that support the JEDEC JESD204 standard (Serial Interface for Data Converters) interface are able to directly connect to one or more FPGA MGT ports.

FMCs deliver a number of compelling design advantages over alternative approaches to optimizing FPGA I/O throughput. Because their simplicity eliminates redundant interfaces and other components, they can maximize data throughput and minimize latency. Their simplicity also provides the system designer with greater control over power, noise, and thermal issues than was possible with either PMC and XMC modules. They can speed time-to-market, too, shortening development cycles for design variations. With FMCs the FPGA design requires minimal, if any, HDL changes to support a new I/O interface. Cost and time savings result when a single FPGA design can be used in multiple applications or programs by simply changing the required FMC module. Perhaps the greatest single benefit that FMC modules offer is the cost savings that come from being able to reuse either FMCs or FPGA carriers, which reduces development costs and recurring costs through the use of fewer components, with higher commonality, across multiple programs.

Examples of new FMC cards, based on the HPE720 (Figure 1), are provided by Curtiss-Wright Controls’ recently introduced ADC511 module along with the ADC512, a dual-channel board, and the ADC513, a quad-channel board. ADC511 is a 400 MSps 14-bit, dual-channel ADC card. The ADC512 is a 3000 MSps per channel ADC FMC Card. And the ADC513 is a 1.5 GSps 8-bit, analog ADC card, which can support up to 1500 MSps data throughput per channel.

Figure 1: The baseboard for recently introduced FMCs from Curtiss-Wright Controls is the company’s HPE720, a 6U VPX hybrid processor board with dual Xilinx Virtex-5 FPGAs and a MPC8641D.

Robert Hoyecki
is Director of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.

Rob can be reached at