EDA vendors roll out advances for 20 nm design
While 28 nm CMOS ICs are still new to the semiconductor market, the design enablement ecosystem is continuing its relentless pursuit of Moore’s Law by preparing tools and building blocks in advance of the next-generation 20 nm technology that will be available for early production sometime in 2013. Unlike the software industry, where a nebulous “public beta” often designates a product that one may use at their own risk, semiconductor foundries such as Taiwan Semiconductor Manufacturing Corporation Limited (TSMC) are more direct in their descriptions. “Risk production” is used in the semiconductor industry to describe the first general availability of a new IC process, following the preceding test chip phase that manufacturers use to wring out a new technology. The 20 nm node will mark an inflection point, as it will be the last point on the nearly 50-year-old scaling trajectory where planar transistor structures will be used.
To squeeze devices in two dimensions one more time, foundries have had to adopt a new technique, Double Patterning Technology (DPT), which will have a major impact on EDA tools and design flows. The challenges are so great that they have delayed the availability of a 20 nm process from TSMC, who had said at their 2012 Annual Shareholder Meeting in June that they were “on track for risk production in the second half of 2012.”
Readying 20 nm technology
At their Open Innovation Platform (OIP) Ecosystem Forum in October, TSMC declared that their 20 nm design infrastructure is now ready. TSMC Vice President of R&D, Dr. Cliff Hou, said that DPT awareness is required throughout 20 nm design flows, in place and route, timing analysis, physical verification, and Design For Manufacturing (DFM). DPT provides a workaround for the limitations of optical lithography, but requires that wires placed at less than approximately 80 nm spacings go through two separate steps to be patterned reliably. First, wires get “colored” by EDA tools during the placement and routing of a design with geometric structures that make up the interconnect assigned to one of the two patterning masks based on heuristic rules for the process. The alignment of those two masks introduces more variability in the process, which must be accounted for for timing closure. Physical verification must take the coloring into account to determine if any layout design rules have been violated. Then, DFM tools that create the actual mask data must combine all of the geometries and add features to each wire as needed to enhance dimensional resolution.
With their OIP Ecosystem, TSMC has adopted an approach to new process development that mirrors those long-used by Integrated Device Manufacturers (IDMs) such as Intel and Texas Instruments, who develop complex designs in parallel to test their new manufacturing capabilities. Since TSMC does not produce their own designs, they have partnered with ARM and other design IP providers to produce a 5 mm x 5 mm x 20 nm test chip SoC based on a Cortex A9 processor core. Dr. Hou said that 20 nm foundation IPs (such as primitive logic cells) are ready now and have been silicon validated, and that specialized IP will be available in Q1 2013.
Award-winning design partners
In keeping with the ecosystem collaboration approach TSMC has fostered with their OIP, the company presented a number of “Partner of the Year” awards to EDA competitors for their contributions to “Joint Delivery of the 20 nm Reference Flow.” Synopsys received an award for IC Compiler physical implementation tools for Power, Performance, and Area (PPA) optimized layouts, the IC Validator DPT coloring engine and rule checker, PrimeTime DPT-aware variation analysis, and StarRC, which includes DPT mask misalignment effects in parasitic extraction.
Cadence also received an award from TSMC for their contributions to the 20 nm flow, which include the Virtuoso custom/analog design platform and Encounter RTL-to-signoff tools. Mentor was also a “Big 3” award recipient for the 20 nm feature capabilities they have added to Pyxis IC Station for custom design, Eldo fast SPICE simulation, their Olympus-SoC DPT-aware place and route system, Calibre nmDRC and PERC physical Design Rule Checkers (DRC) and Electrical Rule Checkers (ERC), and Tessent silicon test products.
New EDA representation
Emerging EDA companies were also represented in TSMC’s 20 nm awards by ATopTech – a newcomer who is taking on Synopsys, Cadence, and Mentor with their Aprisa and Apogee tools included in TSMC’s 20 nm Reference Flow. ATopTech says that Aprisa is a complete DPT and color-aware place and route solution, which employs a hierarchical database on which the company adds analysis engines for parasitic extraction, a DRC engine, and a fast timing engine. Apogee is a top-level physical implementation tool for layout prototyping, floor-planning, and chip assembly. ATopTech provides a hierarchical design flow, which includes technology to aid in performing top-level timing closure during physical chip assembly. ANSYS subsidiary Apache Design was awarded for their contribution of RedHawk and Totem 20 nm IR drop and Electromigration (EM) analysis tools for power, noise, and reliability verification of SoCs and Analog/Mixed-Signal (AMS) designs, respectively.
TSMC also presented design IP Partner Awards at the OIP Ecosystem Forum, but these differ from the EDA Partner Awards in that they are based on feedback from customers of production-proven silicon, therefore older process nodes. Cosmic Circuits won TSMC’s “Analog & Mixed Signal IP Partner of the Year.” Cosmic, based in Bangalore, India and Campbell, California, develops AMS function blocks and subsystems, such as touchscreen interfaces, data converters, audio circuits, and power-management functions. Synopsys received TSMC’s “Interface IP Partner of the Year” award for their DesignWare IP library, which includes USB, PCIe, and DDR memory interfaces, as well as Mobile Industry Processor Interface (MIPI), HDMI audio/video, and Serial Advanced Technology Attachment (SATA) disk drive interface blocks.
The next step: 3D?
The 20 nm story wasn’t the only technology advance that TSMC spotlighted at the OIP Ecosystem Forum. Intel has already moved beyond planar transistors to “3D” FinFET, or Tri-Gate, transistors for their 22 nm process. TSMC plans to do the same at their next process node, with risk production for a 16 nm FinFET process on their roadmap for November 2013, according to COO Dr. Mark Liu.
But before the next process node becomes a reality, TSMC is continuing to develop multi-chip 3D ICs, led by their FPGA partners Altera and Xilinx. The Chip on Wafer on Substrate (CoWoS) process, more accurately described as 2.5D for the use of a silicon interposer, also requires EDA tool innovation to develop a new reference design flow. Some of the issues that arise involve chip-package co-design, testability, and thermal modeling. Along with being cited for their contributions to the 20 nm flow, Mentor Graphics, Cadence Design Systems, and ANSYS-Apache also received awards from TSMC for their contribution to CoWoS Design Enablement.
As has always been the case for Moore’s Law, whenever an obstacle has arisen that seems to stand in the way of further scaling, engineers find a solution to overcome it. The next step is to go vertical, via FinFETs or CoWoS, which will be followed by more widespread use of true 3D die stacking. For EDA vendors, the new design flows present many challenges, but also numerous opportunities for further innovation.