FMC modules deliver high-speed I/O from ADCs to FPGAs

Overcoming the difficulty of designing an FPGA with I/O that suits a variety of applications.

Some MCs in the entertainment world do better than others at communicating with many different kinds of audiences. Now it turns out that “MCs” in the reconfigurable embedded computing world are not all equal either, as Mark points out here, comparing PMCs XMCs, and FMCs with regard to handling I/O interfaces, power, cooling, noise isolation, and other issues.

While interest in reconfigurable embedded computing using FPGAs as I/O processors has continued to grow, design challenges have impeded adoption. One issue slowing the use of FPGAs has been the need for tight coupling between I/O interfaces and these devices. Boards must be designed specifically to handle a particular type of I/O, limiting FPGA design reuse as well as the availability of COTS FPGA boards. Designing an FPGA with the right I/O for a wide range of customers is difficult. Yet another challenge is addressing the cooling and noise isolation required by the analog circuitry on the processing module.

A new mezzanine module, defined by the VITA 57 standard and known as the FPGA Mezzanine Card (FMC), promises to speed and ease the use of FPGAs in embedded systems by eliminating these hurdles. FMC modules enable I/O devices that reside on an industry standard VITA 57 mezzanine card to be attached to and directly controlled by FPGAs that reside on a host board. About half the size of a PMC mezzanine module (Figure 1), an FMC reduces I/O bottlenecks, increases flexibility, and eliminates redundant interfaces, saving costs. To maximize data throughput and minimize latency, the FMC connector’s numerous I/O pins support high-speed signals for moving data between the FMC and the FPGA.

Figure 1: With FMC modules, FPGAs on a host board control I/O devices that reside on an industry standard VITA 57 mezzanine card.
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Open standard mezzanine cards such as PMC, and more recently XMC, have provided an industry standard mechanism for modular and flexible I/O design for 3U and 6U VPX and VME single board computers. Embedded developers have designed extensively with PMC/XMC form factors, but have not found PMCs and XMCs to be optimal for modular FPGA designs: limited board real-estate and severe power and cooling limits make them less than ideal FPGA-based I/O platforms. In addition, the industry-standard PCI, PCIe, and Serial RapidIO interfaces that most basecards provide to a PMC or XMC site are generally complex and take up valuable logic resources inside the FPGA.

To address the aforementioned shortcomings, the FMC standard supports a flexible, modular I/O interface to an FPGA located on a baseboard or carrier card. Using an approach that divides the design into a carrier and a mezzanine, the FMC allows the physical I/O interface portion of the design to be decoupled from the FPGA portion while maintaining a close physical connection between the physical I/O interface and the FPGA. The carrier contains one or more FPGAs and associated functionality and forms a common platform from which one can base numerous I/O platforms. The mezzanine contains the actual I/O components. In this way completely new I/O modules can be created simply by designing a new FMC module. This standards-based method for fielding flexible I/O modules allows systems integrators to mix-and-match these FMC modules on common carriers to achieve the ideal I/O mix for their applications.

The carrier contains one or more FPGAs and the associated functionality that will always be common to any variation of the board design. The mezzanine contains the functionality that can be variable within a board design, such as the I/O portion of the design.

The FMC card enables the system designer to separate the FPGA computational portion of an I/O mechanism from the transmission and reception circuitry. In the case of an ADC card, the analog to digital circuitry is located on the FMC, but the computation and operation that must be done to the converted analog data, such as digital downconversion or reformatting the data to send over a fabric or bus, is performed by the FPGA device located on the base card. This approach delivers two particular advantages. First, separating the analog circuitry from the computational stage simplifies the design of the mezzanine card by making power, cooling, and noise isolation much less complex. Second, product flexibility it increases.

In a traditional FPGA-based ADC PMC or XMC board design, the designer would have to address the design of the ADC front-end to the FPGA, the attached memory, and all connections to the base card. Accommodating a new ADC with a different level of performance would require the entire process to be undertaken again, virtually from scratch, as the placement of the new devices and power supplies would invariably change.

With FMCs the ADC portion of the design remains on the FMC card, minimizing any required changes to the base board. It’s possible to design new FMC mezzanine cards quickly and more cost-effectively while reusing a common base board for a wide range of I/O port types. This simplifies the use of different front ends for different programs while preserving investments in the basecard. As new I/O types come to the fore there is no need to replace the costly carrier card. At the system-level, designers using FMCs have more control over power, noise, and thermal issues than possible with PMC and XMC modules.

Another advantage of FMCs is they support much more FPGA-based processing resources on a carrier card, allowing much more processing to be done, and so reducing the need for data reduction or decimation. PMCs and XMCs are limited by their use of the PCI and PCI Express buses respectively and are often confronted with bandwidth that exceeds their capacity. In such cases the data must first be reduced within the FPGA.

The FMC standard defines an I/O mezzanine module that works intimately with an FPGA. The standard defines two widths – single and double. The single-width module measures 69 x 76.5 mm, and is approximately half the size of a PMC module, supporting a single connector, P1, to the carrier. The double-width module measures 139 x 76.5 mm and Figure 2 (provided courtesy of VITA) shows that it can support one or two connectors to the carrier, P1 and P2.

Figure 2: FPGAs work closely with an I/O mezzanine module, which comes in two FMC standard defined widths – single and double.
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Two connector choices are available to interface the FMC to an FPGA on a carrier: a Low Pin Count (LPC) connector with 160 pins and a High Pin Count (HPC) connector with 400 pins. The VITA 57 connector was chosen to ensure developers have the functionality and performance they need to allow them to move their I/O to a mezzanine card. The connector is designed to support single-ended and differential signaling up to 2 Gbps and signaling to an FPGA's Multi-Gigabit Transceivers (MGTs) up to 10 Gbps. The LPC connector provides 68 single-ended user-defined signals or 34 user-defined differential pairs. The HPC provides 160 single-ended user-defined signals or 80 user-defined differential pairs.

To FMC connector can support very high bandwidths; a single differential pair can provide 2 Gbps of bandwidth when clocked at 1 GHz, as data can be transferred between the FMC and the carrier on the rising and falling edges of the clock. Utilizing 48 differential pairs (12 bits/ADC x 4) of the HPC connector clocked at 107.5 MHz (one half of the ADC sampling rate) would provide the required bandwidth to move the data from the four ADCs into the FPGA on the carrier.

The FMC modules MGT interfaces support multigigabit serial links. Moving the copper connectors or fiber optic transceivers from the base-FPGA design to an FMC mezzanine card makes it much easier for a single FPGA design to support various physical interfaces. Next-generation ADC and DAC chips that support the JEDEC JESD204 standard (Serial Interface for Data Converters) interface will directly connect to one or more FPGA MGT ports.

Figure 3 is an example of a new FMC module, the ADC512 card was recently announced from Curtiss-Wright Controls Embedded Computing. Designed for use with Curtiss-Wright Controls’s FPE650 (Quad FPGA 6U VPX), HPE720 (MPC8641D/dual FPGA 6U VPX) and FPE320 (3U FPGA VPX) host cards, the ADC512 provides high-bandwidth I/O direct to the host board’s FPGA(s). This FMC delivers high sampling rate and high bandwidth for use in demanding direct RF downconversion, SigInt/Surveillance, satellite communications, and Software-Defined Radio applications. The ADC512, a 3GSps 8-bit, dual channel ADC card, is able to support up to 6 GBps data throughput. It speeds and simplifies the integration of FPGAs into embedded system design by providing high-bandwidth I/O direct to the host card’s FPGAs. The module eliminates data bottlenecks to increase DSP subsystem performance by routing high-speed ADC I/O directly to the host board’s FPGAs via the FMC connector.

Figure 3: A 3 GSps 8-bit dual channel ADC card, the ADC512 card, is a new FMC module from Curtiss-Wright Controls Embedded Computing.
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The ADC512 has two onboard National Semiconductor ADC083000 ADC devices, each of which supports a sampling rate up 3000 MS/s per channel. By routing the ADC device interfaces directly to the FMC connector, the ADC512 enables an FPGA on the host board to directly control and receive data. The ADC512 supports an external clock input to control the sampling rate for both ADC channels Input and output triggers are provided enabling the number of input channels to be increased by synchronizing multiple ADC512 modules.

As the adoption of FPGA-based computing continues to grow, so too will the need for high-performance I/O connected directly to these FPGAs. FMCs provide a flexible, standards-based solution for systems employing FPGAs for high-performance I/O processing

Mark Littlefield is the Product Marketing Manager for Curtiss-Wright Controls Embedded Computing's FPGA computing products. He has more than 15 years of experience in the embedded computing industry, first as an engineer developing robot vision systems for NASA, then later as a field applications engineer, technical program manager, and product manager. Mark has a BS and an MS in Control Systems Engineering from the University of West Florida.


Curtiss-Wright Controls Embedded Computing