FPGA technology fueling Software Defined Radio

Current-generation technology enables reconfiguration of the hardware partitioning of an SDR-based 3G base station to support multiple standards (see Figure 1). To reconfigure the entire system, the ideal SDR base station would perform all signal processing tasks in the digital domain. However, current-generation, wideband data converters cannot support the processing bandwidth and dynamic range required across different wireless standards. As a result, the A/D converter and D/A converter usually operate at Intermediate Frequency (IF). Separate wideband analog front ends execute subsequent signal processing to the Radio Frequency (RF) stages, as shown below.

Figure 1

Digital IF processing
Digital IF extends the scope of digital signal processing beyond the baseband domain out to the antenna, the RF domain, which increases system flexibility while reducing manufacturing costs. Moreover, digital frequency conversion provides greater flexibility and higher performance, in terms of attenuation and selectivity, than traditional analog techniques. Data formatting – often required between the baseband processing elements and the up converter – can be seamlessly added at the front end of the up converter as shown in Figure 2. This technique provides a fully customizable front end to the up converter and allows for channelization of high-bandwidth input data, which is found in many 3G systems. Custom logic or an embedded processor can be used to control the interface between the up converter and baseband processing element.

Figure 2

Digital up converter
In digital up conversion, the input data is baseband filtered and interpolated before it is quadrature modulated with a tunable carrier frequency. To implement the interpolating baseband Finite Impulse Response (FIR) filter, a proprietary FIR compiler can build optimal fixed or adaptive filter architectures for a particular standard through speed-area tradeoffs. An accompanying Intellectual Property (IP) core can generate a wide range of architectures for oscillators with spurious-free dynamic range in excess of 115 dB and very high performance. Depending on the number of frequency assignments to support, the right number of digital up converters can be easily instantiated in a Programmable Logic Device (PLD).

Crest factor reduction
3G Code-Division Multiple Access (CDMA)-based systems and multi-carrier systems such as Orthogonal Frequency Division Multiplexing (OFDM) exhibit signals with high crest factors (peak-to-average ratios). Such signals drastically reduce the efficiency of PAs used in the base stations. Proprietary FPGAs offer a reconfigurable platform for SDR base stations to implement Crest Factor Reduction (CFR) techniques customized to each standard.

Digital predistortion
The 3G standards and their high-speed mobile data versions employ non-constant envelope modulation techniques such as Quadrature Phase-Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM). This places stringent linearity requirements on the power amplifiers. Digital Predistortion (DPD) linearization techniques, including both Look-Up Table (LUT) and polynomial approaches, can be efficiently implemented using high-performance FPGAs. The multipliers in the DSP blocks reach speeds up to 380 MHz and can be effectively time-shared to implement complex multiplications. When used in SDR base stations, these FPGAs can be reconfigured to implement the appropriate DPD algorithm that efficiently linearizes the PA used for a specific standard.

Digital down converter
On the receiver side, digital IF techniques can be used to sample an IF signal and perform channelization and sample rate conversion in the digital domain. Using under-sampling techniques, high frequency IF signals, typically 100+ MHz, can be quantified. Proprietary Digital Down Converter (DDC) reference designs can be used as a design starting point or experimental platform. For SDR applications, since different standards have different chip/bit rates, non-integer sample rate conversion is required to convert the number of samples to an integer multiple of the fundamental chip/bit rate of any standard. (See Figure 3.)

Figure 3

Baseband processing
Wireless standards are continuously evolving to support higher data rates through the introduction of advanced baseband processing techniques such as adaptive modulation and coding, Space-Time Coding (STC), beam forming, and Multiple Input Multiple Output (MIMO) antenna techniques. Baseband signal processing devices require enormous processing bandwidth to support such computationally intensive algorithms. Proprietary FPGAs are tailored for applications such as channel coding for HSDPA and beam forming. The baseband components also must be flexible enough to enable SDR functionality that is required to support migration between enhanced versions of the same standard, as well as the capability to support a completely different standard.

Coprocessing features
As illustrated in Figure 4, SDR baseband processing often requires both processors and FPGAs, where the processor handles system control and configuration functions while the FPGA implements the computationally-intensive signal processing data path and control, minimizing the latency in the system. To go between standards, the processor can switch dynamically between major sections of software while the FPGA can be completely reconfigured, as necessary, to implement the data path for the particular standard.

Figure 4

Proprietary FPGA coprocessors interface with a wide range of DSP and general-purpose processors providing increased system performance and lower system costs. Complete proprietary system builder software can facilitate coprocessor integration, enabling designers to assemble parameterized blocks representing a plethora of functions ranging from muxes through fully parameterized FIR filters. Once a dataflow system has been captured, it can be exported for use as a coprocessor in any processor-based system assembled by the system builder software.

SDR for defense applications
SDR is the underlying technology behind the Joint Tactical Radio System (JTRS) initiative to develop software programmable radios that can enable seamless, real-time communication across the United States military services, and with coalition forces and allies. The functionality and expandability of the JTRS is built upon an open architecture framework called the Software Communications Architecture. The JTRS terminals must support dynamic loading of any one of more than 30 specified air-interfaces or waveforms that are typically more complex than those used in the civilian sector. Altera FPGAs have the necessary processing power and flexibility to address such requirements. Altera is also a member of the SDR Forum and is actively involved in contributing to the growth of SDR technology.

SDR crucial to future success
SDR technology is crucial to the future success of wireless technology involving multiple applications, from digital IF and baseband processing to coprocessing and military communications. SDR enables wireless devices to support multiple air-interfaces and modulation formats via a reconfigurable hardware platform across multiple standards. FPGAs, with their flexible design functionality and device reconfigurability, are playing a key part in bringing this SDR technology to fruition.