FPGAs and DSP are hot topics at the Hot Chips Conference

The Hot Chips Conference, which is organized under the auspices of the IEEE Computer Society’s Technical Committee on Microprocessors and Microcomputers and the ACM Special Interest Group on Computer Architecture, will be held on August 27-29. As in past years, the conference will begin with a pair of tutorials on the first day, followed by presentations from companies and a few universities that are developing some of the industry’s most advanced processors across a broad range of applications. The event will have many sessions applicable to FPGA and DSP designers.

OpenCL gaining traction

A tutorial on “The Evolution of Mobile SoC Programming” that opens the Hot Chips Conference should be of interest to FPGA designers, as it will be presented by a speaker from the Khronos Group, which is fostering the development of OpenCL for parallel programming of heterogeneous multiprocessors. FPGA vendors Altera and Xilinx are both exploring use of the language to support their new generation of FPGA SoCs.

In his Semicon West Keynote presentation on July 11, Xilinx CTO Ivo Bolsens put forth OpenCL as a solution to what he called the “Future Challenge of Hardware and Software Co-design.” The language is designed to enable the programming of a mix of processors, such as the ARM cores and DSP engines in FPGA SoCs. OpenCL could help overcome the barrier of HDL-based FPGA design methodologies, which is foreign to many software engineers. At Semicon, Bolsens illustrated how OpenCL could enable software engineers to continue using familiar commercial tools for C-programming of the ARM processor system, while functions that are intended to be executed on FPGA hardware could (in parallel) be used as inputs to an Electronic System Level (ESL) design flow. With OpenCL, a High-Level Synthesis (HLS) tool would create the application-specific hardware accelerator functions without requiring any HDL programming. Altera demonstrated such an OpenCL-to-ESL flow at the DESIGN West show earlier this year.

Stacking on the IC tech news

The Monday afternoon Hot Chips tutorial on Die Stacking also has an FPGA component, with presentations by AMD, Amkor, SK Hynix, and Xilinx scheduled. Die stacking, or 3D IC technology, was also a hot topic at Semicon West, where Altera discussed their collaboration with semiconductor foundry TSMC on a 2.5D IC process called Chip-on-Wafer-on-Substrate (CoWoS). In March, Altera announced they had built a heterogeneous test vehicle with the process.

Xilinx has been first to market, with multi-FPGA die based on their 2.5D Stacked Silicon Interconnect (SSI) technology. The Xilinx Virtex-7 2000T provides capacity for up to two million logic cells by connecting four 28 nm FPGAs in a single package using a silicon interposer. Xilinx announced a heterogeneous multi-chip product in May, the H580T, which combines an FPGA die with a separate 28 Gbps transceiver die in the same package. This device will be the subject of Xilinx’s end-of-day presentation on Tuesday at Hot Chips, “FPGAs with 28Gbps Transceivers Built with Heterogeneous Stacked-Silicon Interconnects.”

We can expect to see more use of 2.5D manufacturing to mix-and-match ICs with FPGAs for higher performance programmability.

The next round of ASICs vs. FPGAs

In the Tuesday morning Hot Chips session on Fabrics & Interconnects, Solarflare is scheduled to present “FPGA Augmented ASICs: The Time Has Come.” Solarflare is a developer of solutions for high-performance, low-latency 10 GbE server networking. In February, the company announced development of their ApplicationOnload Engine (AOE), which employs FPGA accelerators to augment a 10 GbE server adapter, for applications that require real-time, high-performance network data. This topic is likely to re-ignite the ASIC vs. FPGA debate, which took place at the 2012 Design Automation Conference (DAC) in June.

An advanced vision for FPGAs and DSP

Wireless base stations and embedded vision are two application spaces that are pushing the performance of both FPGAs and DSPs, and each will be well represented at the Hot Chips conference. In a session on Multimedia and Imaging, Analog Devices (ADI) will describe their “BF60x Vision Focused Digital Signal Processor SOC.” ADI also presented their BF60x DSPs at the Embedded Vision Alliance (EVA) event, which was held in conjunction with DESIGN West earlier this year (EVA will be holding a similar event at DESIGN East in September). ADI optimized their devices for embedded vision applications by integrating a video subsystem, which offloads image processing tasks from the general-purpose DSP cores. Toshiba will also be presenting in the Multimedia and Imaging session on “A Heterogeneous Multi-Core SoC for Image-Recognition Integration.”

DSP on the go

There will be one more talk on FPGAs at Hot Chips, which is also applicable to DSP, when Altera presents “Floating-Point Matrix Processing using FPGAs.” Focus will shift to DSP for mobile, wireless applications following a keynote on “The Future of Wireless Networking” by      Alcatel-Lucent. In the SoC session, Cavium will lead off with “High Performance and Efficient Single-Chip Small Cell Base Station SoC,” which will be immediately followed by Qualcomm presenting “FSM (Femtocell Station Modem) – A highly integrated, performance driven, chipset solution for the small cell market.” Finally, Intel will review their “Medfield Smartphone - Intel's ATOM Z2460 Processor,” the competitor to ARM’s current dominance of the smartphone application market, with devices designed by companies such as Qualcomm, NVIDIA, TI, and Samsung.

Catch the highlights

If you won’t be able to attend the Hot Chips Conference in Cupertino later this month, look for reports of the presentations I have previewed here on DSP-FPGA.com, and in my 4G Focus column for CompactPCI, AdvancedTCA & MicroTCA Systems.

For more information, contact Mike at mdemler@opensystemsmedia.com.