FPGAs can lead the way to next-generation technology

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FPGAs can lead the way to next-generation technology

At GLOBALFOUNDRIES’ 2nd annual Global Technology Conference (GTC) in August, Mojy Chian, Senior VP for Design Enablement at the company, posed this statement and follow-on question to a panel that included Electronic Design Automation (EDA) executives and the CEO of ARM:

“Process technology has primarily been driven by high-volume products. Over the past decade, other than microprocessors and FPGAs, consumer mobility has been driving migration to the next process geometry. Do you expect this trend to continue?”

With the EDA industry heavily focused on Application-Specific Integrated Circuit (ASIC) design, it may be no surprise that the respondents overlooked the FPGA statement in their answers. Most semiconductor industry followers are well aware of the role that mobile devices now play in driving the semiconductor ecosystem. Memory chips and microprocessors for the PC market have been joined, if not surpassed, by Systems-on-Chip (SoCs) for smartphones as the primary forces pushing manufacturers in their efforts to extend Moore’s Law to the next process node. But what of FPGAs? How did field programmable devices come to be included in this group of leading-edge IC applications?

FPGAs are often described as a lower-cost alternative to ASICs, but that only tells part of the story. There’s no argument that, with an ASIC mask set estimated to cost approximately $6 million at the currently leading-edge 32 nm technology node (according to a white paper by authors from IBM, PDF Solutions, and Carnegie Mellon University), only the highest volume applications can justify Customer-Owned Tooling (COT). But if cost is the only consideration, designers can just stick to using an older process node. Evidence suggests that many are doing just that, as GLOBALFOUNDRIES reported deriving nearly a third of their first-half 2011 revenues from 65/55 nm devices, and an equivalent share from designs that are implemented in even older technologies at 90 nm to 180 nm and larger.

A more accurate explanation for why FPGAs have become drivers of process technology is not just their lower cost compared to ASICs, but also because of the advantages that can be derived from their cost-performance. Today’s most advanced applications require the higher performance and functional density that only smaller geometry transistors can deliver. FPGAs are now leading the way in providing more designers with the earliest access to the benefits of advanced process nodes, while mitigating the cost of custom tooling.

Two performance areas where FPGAs often surpass ASIC solutions are the integration of specialized Digital Signal Processing (DSP) functions and high-speed Input-Output (I/O) interfaces. For example, Altera Corporation recently rolled out a new signal integrity development kit for the Stratix V GX FPGA, which provides designers with access to 28 nm technology. You can use the Stratix V GX Serializer-Deserializer (SERDES) to develop transceiver links for high-bandwidth applications ranging from 600 Mbps to 12.5 Gbps. Users of the kit can verify compliance with popular communication protocol standards, including 10 GbE; 10GBASE-KR; PCI Express (PCIe) Gen1, Gen2 and Gen3; Serial RapidIO; Gigabit Ethernet (GbE); 10 GbE XAUI; CEI-6G; CEI-11G; HD-SDI; Interlaken; and Fibre Channel.

In the DSP-FPGA realm, Xilinx has been active in developing intellectual property cores for heavy-duty image processing applications in High-Definition (HD) television production applications. In their latest round of enhancements, the company announced (at the IBC Conference in September) the addition of support for the -5 and -6 revisions of the Society of Motion Picture and Television Engineers (SMPTE) 2022 standard for transporting uncompressed HD and 3D high-resolution video packets over Internet Protocol (IP) networks. Engineers can combine the 2022-5/-6 cores with Xilinx 10 GbE I/Os to enable the transmission of live packet video over IP networks directly to the production studio. Video over IP eliminates the cost of rolling trucks and heavy cables to an event, and also offers a “greener” solution for lower environmental impact. The hardware acceleration, which Xilinx provides in the SMPTE cores, also enables real-time HD video editing. Xilinx is initially introducing the SMPTE 2022 cores in the company’s 40 nm Virtex-6 FPGAs. A 28 nm Kintex-7 implementation of SMPTE 2022 is planned by Xilinx for availability sometime in 2012.

However, while FPGAs continue to push the performance envelope, issues remain that hold back more widespread adoption. At the 2011 IEEE Custom Integrated Circuits Conference, University of California at Berkeley professor (and BEEcube founder) John Wawrzynek gave a poor report card to FPGAs and the supporting EDA tools, at least in comparison to microprocessors and Graphical Processing Units (GPUs), for reconfigurable computing. Professor Wawrzynek cited the lack of support for high-level programming models and languages in FPGAs as the #1 problem. The design process for FPGAs is much akin to ASICs, he said, with a flow that requires a design description in a Verilog or VHDL hardware description language followed by a too slow (eight hours long in one example) place and route. “Slow place and route is a major hindrance, it’s not just an annoyance,” said Professor Wawrzynek. Higher-level C-language-based synthesis tools, such as the Synfora platform (acquired by Synopsys) or AutoESL (acquired by Xilinx) help, but still require that designers modify their C/C++ with hardware implementation in mind in order to be synthesizable. There is also no support for multicore parallel processing.

FPGA vendors are working on making programmable devices that can, at least partially, support a more familiar microprocessor-like programming model. The Xilinx Zynq-7000 Extensible Processing Platform combines an ARM dual-core Cortex-A9 MPCore processing system with a 28 nm programmable logic architecture on the same chip. The programmable fabric is provided with more than 3,000 interconnects to the processing system, much like a two-chip Application Specific Standard Processor (ASSP) combined with an FPGA. Professor Wawrzynek said his research team is looking at Zynq, and that they really like the combination of a processor with an FPGA to enable use of all the existing infrastructure of compilers and operating systems that can be combined with the programmable elements for customized accelerators. If the FPGA and EDA vendors can improve the hardware design tools and enhance ease of use, we can expect FPGAs to become the preferred method for more designers to access the coming generations of semiconductor technology.

For more information, contact Mike at mdemler@opensystemsmedia.com.