Getting higher resolution analog signals into the digital domain
Why conventional CPU configurations cannot reach the level of processing performance and potential I/O bandwidth the latest FPGA iterations can.
Rob explains how baseboard FPGAs and FPGA Mezzanine Card (FMC) I/O cards are teaming up with bigger FPGAs and the new industry standard FMCs (ANSI/VITA 57.1) for a new generation of ADCs. System designers are building open standards-based board systems where ADC and DAC capabilities are directly coupled to an FPGA-supplied processing element.
Modern radar, ECM, and SIGINT applications have an unquenchable thirst for good quality data because this will ultimately define the limitations of the system. In the analog domain, the simplest limitation may be resolution (or sensitivity), which defines parameters such as range or weather or selectivity. Latency is another key consideration. If you can’t respond fast enough to the threat, the quality of the data isn’t going to help. For example, the trend for ADCs, not surprisingly, is increased resolution at higher and higher sample rates (and bandwidths). Today, ADC technology is firmly located in the L-band spectrum, with commercial ADCs approaching 4 GSPS at 12-bit resolution. Such performance levels, with useful resolution, are important for applications such as telecommunications and radar. At these frequencies channelizing can be done in the processor, lessening the requirement for down conversion prior to data sampling. Removing some of the down conversion stages can save cost and power, while increasing performance and flexibility. Even 16-bit converters are boasting speeds as high as 250MSPS at the leading edge, which requires careful backend architectures.
The design challenge at these high data rates is how to interface these newly obtainable levels of resolution to the digital domain, a task that traditional processors can’t handle. The answer is a combination of baseboard FPGAs and FPGA Mezzanine Card (FMC) I/O cards. When combined with larger FPGAs and the new industry standard FMCs (ANSI/VITA 57.1), the new generation of ADCs (Figure 1 shows one such ADC, the Curtiss-Wright Controls Embedded Computing ADC-510) is enabling system designers to integrate open standards-based board systems in which both ADC and DAC capabilities are directly coupled to the processing element, provided by the FPGA. The result is an order of magnitude improvement in latency from input to output.
The technical hurdles to obtaining high quality data by improving resolution and latency include increasing the data bandwidth infrastructure and using fast processors to deal with it. However, built-in flexibility to track and adapt to newer ADCs is also important. The challenge is complex. If the application requires several channels, as might be needed for modern beamformers, the data rates range from 10 to 100s of Gbps with a need for careful synchronization and low jitter (another source of noise to be discussed in a future column).
The newest generations of FPGAs present developers with a level of processing performance and potential I/O bandwidth that conventional CPU configurations can’t easily match. Solving the dual problem of how to maximize I/O bandwidth while still being able to change the I/O functionality, the FMC directly addresses the challenges of FPGA I/O. The direct link between the FPGA processing element and I/O minimizes latency. FPGAs as a processing element have grown large enough to perform large FFTs, high channel count digital down conversion, and even practical floating-point processing, important in tasks such as pulse compression.
FMC modules take advantage of the intrinsic I/O capability of FPGAs to separate the physical I/O functionality on the module from the FPGA board design of the module’s host, while maintaining direct connectivity between the FPGA and the I/O interface. This approach is simpler because FMCs only host I/O devices, such as ADCs, DACs, or transceivers. And FMC modules have no on-board processors or bus interfaces, such as PCI-X. As a mezzanine card focussed on the I/O and not on unnecessary busses, the FMC is straightforward and simple to replace when newer devices become available. The FMC format helps to solve the issues of flexibility, latency, and bandwidth. An FMC is similar in height and width to a PMC, but almost half the length. The reduced width compared with PMC or XMC enables up to three FMCs to be fitted to a 6U host.
Even better for space-, weight- and power-constrained embedded systems, the increased bandwidth of the new ADC devices does not come at the cost of a comparable rise in power consumption. We are seeing these devices with power dissipation rated near 2W per converter, which means that a quad-channel FMC will require less than 10W.
In the near future we expect that the new generations of 28nm FPGAs, predominantly from Xilinx and Altera, will deliver significant improvements in performance, bandwidth, connectivity, and power that will enable ever more sophisticated systems to take advantage of FMCs for new generations of baseband I/O receivers.
Robert Hoyecki is Vice President of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.
Rob can be reached at firstname.lastname@example.org.