Latest FPGA tools keep getting better, smarter

Tightening the grip on faster and easier development

More intuitive integration and the realization of multiple embedded processors, plus safety certification, highlight tools’ new features.

FPGAs are no longer just glue logic. Let’s face it, designing an FPGA requires a multi-disciplined designer who’s part RTL coder, system engineer, and software writer. The latest FPGA development tools from Altera and Xilinx are designed to simultaneously solve more real-world design problems, while dramatically improving ease-of-use. If you or your company implements FPGA designs – especially those used for DSP systems – you’ll want to make note of these latest tools and development systems.

Xilinx: The end of a la carte

Xilinx finally recognizes that its battle is not against gate arrays, it’s against companies designing ASSPs such as those for handheld music players, medical devices, or deployed military platforms. As long as the volume isn’t in the tens of millions, chances are an FPGA will be used instead of a custom IC. But those target systems usually fall into several easily-identified domains with known-in-advance IP such as MPEG4 decoders or 1024-point FFT algorithms. As well, the company’s smorgasbord of design tools was a dog’s breakfast of synthesis, floor-planning, probe, IP core, and reference designs that mostly represented a closed system – and even then, most tools didn’t play well together.

By the time you read this, Xilinx will have gotten religion and announced ISE Design Suite 11.1. The new “Domain-specific Methodology for Targeted Design Platforms” creates four pre-packaged toolboxes with individual products designed for interoperability, improved performance (both in the software and in the final FPGA design), and tailored for the types of design problems engineers and actually battling. Figure 1 shows the various editions and their major tool components.

Figure 1: Xilinx’s ISE Design Suite 11.1 now has four “Design Platform” flavors.
(Click graphic to zoom by 1.9x)

You might be thinking that on the surface this is just a repackaging exercise, especially since the lower end Logic platform is the basis for the others, and more tool components just get tacked on as you add Embedded, DSP, and finally the full monty System platform. But you’d be wrong. Now that Xilinx has defined the types of customers using all this stuff, ISE is better suited to solving problems. As well, new features have been added to simplify what engineers are actually designing. In the Embedded platform, for instance, Xilinx acknowledges that a full 20 percent of its customers are using an embedded CPU such as the PowerPC, soft MicroBlaze, or an ARM (in select silicon versions). So the Embedded platform includes multiprocessor support (but not cache coherency) and cross-optimization with a multiport memory controller that uses fewer resources and less silicon.

In the DSP platform, System Generator automatically launches the SDK to modify software when using an embedded processor, allowing designers to code algorithms in the CPU, in ExtremeDSP slices, or in logic. The AccelDSP tool is now included and can deliver over 2x higher performance in Virtex-5 (and soon) Virtex-6 silicon. And interestingly, an Enhanced Fixed Point report helps designers decide the tradeoffs in moving from floating to fixed point math. There’s lots more to ISE 11.1 than we can cover here.

Across the board, ISE 11.1 is supposed to deliver 10 percent lower dynamic power by reducing the number of switching elements and gated clocks. It promises 2x faster runtimes, while delivering 28 to 30 percent better host memory utilization (the difference between a low cost or big bucks machine). As well, Xilinx has finally (!) implemented a FLEXnet license system with either floating or locked (cheaper) options. As well, the company is aligning the 25 development reference boards developed for the Platform-oriented Virtex-5 devices into Design Platform versions, complete with an industry-standard FMC mezzanine card interface.

Altera: 40 nm and still shrinking

In February, Altera followed up on last year’s 40 nm news by making it official: Stratix IV GT and Arria II GX have screaming transceivers. Capable of pumping 155 Mbps up to a whopping 11.3 Gbps, the high-end hardware in Stratix IV GT brings to bear 24 high speed transceivers, and an additional 24 6.6 Gbps transceivers, all in a density with up to 530K LEs, 20.3 Mbits of RAM and 1,288 18 x 18 multipliers for DSP implementations. So that’s the hardware; what about the tools?

Altera has made numerous changes and improvements to the company’s (mostly) free Quartus II software, now at version 9.0. Many of the changes are specifically geared to optimize high-speed transceiver designs in the Stratix, Arria, and HardCopy FPGA families. In fact, this is a major advantage of Altera’s own tool versus a third-party broadline EDA suite: Quartus II version 9.0 is unified across the company’s entire product line. Designers use one familiar software suite for any IC within Altera’s portfolio, which probably saves learning curve time while allowing hardware optimization for low-cost, speed-sensitive, or eventual high-volume ASIC-like HardCopy designs.

New features in version 9.0 include a Simultaneous Switching Noise (SSN) tool that warns a designer of possible pin assignment cross-talk with the high-speed transceivers. While it seems obvious that high-frequency buses shouldn’t all switch at the same time (hello?), routing complex signals while optimizing board real estate could easily result in switching violations. We think this is a nice feature. New metastability analysis capability tools will auto-recognize potential metastability issues, and the TimeQuest static timing analysis tool is now automated to report MTBF values. Finally, the pin planner’s clock network view helps to better manage resources. The company also juggled around some of the previous built-in feature packages. ModelSim Web Edition is now included in Quartus II 9.0 as “Starter Edition,” which Altera says increases simulation speeds by 50 percent. The ModelSim Altera Edition is also available standalone, with another 33 percent speed improvement on top of Starter Edition.

On the DSP side of the house, the company has partnered with The MathWorks in a series of “Military, Aerospace and Defense DSP Productivity Seminars,” showcasing model-based design. Both companies will delve into their DSP design flows in a Stratix IV GX realizing a sustained 175 GMAC sensor fusion application. The customer-location seminar schedule can be found at


As we went to press, Altera announced the Transceiver Signal Integrity Development kit for the Stratix IV GX. With 8.5 Gbps transceivers, the board includes an FPGA, 8 channels routed to SMA connectors plus USB, flash memory, and user software via a GUI that lets designers try out designs for applications such as video over IP, 4G wireless, and digital TV.

Chris A. Ciufo