Latest ADCs will cut IF sampling down to nanoseconds

Rob takes us through the steps that have led to receiver sampling systems being able, for the first time, to use COTS technology, as COTS systems demonstrate their ability to meet rigorous demands.

There are key moments when technology breaks through certain performance barriers and opens up new possibilities in terms of practical and feasible solutions; the speed and resolution of a new generation of ADCs for the EW community is one worthy of note as it equates to probability of survival.

Based on general industry roadmaps, ADC devices sampling in the near future are becoming increasingly attractive for the Electronic Warfare (EW) community. The newer generations of device are ideally suited for direct sampling of wideband Receiver Intermediate Frequency (IF) with greater signal resolution and bandwidth. Today’s high resolution ADCs typically top out at around 200MS/sec. The new devices are expected to offer up to 250Ms/sec performance. When combined with FMCs and FPGAs these new ADC devices will comprise a potential game changer in the military receiver industry, enabling a significant increase in the range, sensitivity, and selectivity of receiver systems to improve operational effectiveness. This operational effectiveness can be quantified in such terms as the Probability of Survival in a combat zone or the Probability of Intercept and characterization of a signal in the SIGINT community.

Signal processing in the digital domain is an important factor in the performance of an EW receiver system (e.g., improved filter performance). The transformation of the signal into the digital domain as early as possible, with an appropriate bandwidth and resolution, is important to the overall system capability. Many EW receivers operate with an IF centered around 160 MHz. A sub-Nyquist sampling strategy with sampling frequency of 213.3 MHz would be the optimum sampling rate for a converter. If the anti-aliasing filter, located prior to the converter, is coupled with the appropriate sampling rate it eliminates interference with the desired signal. This strategy would more than adequately cover the signal bandwidth coupled with the typical narrow band or wide band IF output. Indeed, when using the new higher performance ADCs it may be possible to oversample a narrow band IF thereby further enhancing resolution.

Given the importance of digital transformation and the required sampling frequency, consider the effect of improved sensitivity:

If the one-way radar (signal strength) equation is rearranged to calculate the maximum range of ESM receivers, the received signal equates to the minimum detectable signal (SMin), and the Maximum Range (RMax) is as shown in Equation 1.

Equation 1
(Click graphic to zoom by 2.2x)

Therefore -10logSMin is proportional to 20 log RMax. To put it another way, for a 6dB sensitivity increase, the range is doubled.

The next generation of ADC from major vendors is expected to provide 250Ms/sec with 16-bit resolution. Today's status quo is 14-bit resolution, so this gives us a theoretical 6dB increase in sensitivity. Although this improvement may not necessarily be fully achievable in practice, there will be an inevitable increase in sensitivity by a significant margin.

Those extra few dBs of resolution will enable customers within the EW world to perform more effectively. For example, the ELINT community can take advantage of the improved resolution to perform Single Emitter Identification (SEI) more accurately and at greater range.

The Electronic Countermeasures (ECM)/ES world will be able to detect targets earlier and react more quickly to encountered threats, thereby improving the Probability of Survival. They will also be able to identify the threat type with a higher probability earlier in the engagement.

A COTS first

Historically, receiver sampling systems technology advances have required custom designs in order to effectively process and react to the resulting data. Today, with the emergence of new embedded computing standards that can meet the rigorous demands of these environments and have the infrastructure to match, it’s possible for the first time to use COTS technology.

Rapid deployment of new technology can be achieved utilizing industry standard form factors such as FMC and XMC boards on standard VPX host cards. In the case of FMC, its simplicity, yet high performance profile, allows for even faster development turnaround allowing technology to be tracked more effectively. These industry standard systems offer the capability of providing the sensor I/O capability, the processing of that data into useable information, and the high-speed infrastructure to be able to use the information effectively. Industry standard solutions can even address the low-jitter reference clocks the digitization synchronization process needs.

(Figures 1, 2, and 3, courtesy Curtiss-Wright Controls Embedded Computing, show example cards.)

Figure 1: FMC-XCLK2 Clock – 50-2000 MHz+ Clock Gen

Figure 2: ADC511 ADC – 2x 400MSPS 14b

Figure 3: FPE 320 – Xilinx Virtex-5 3U VPX Processor with FMC Site


As an alternative to an I/O card, a low infrastructure form factor such as an FMC mezzanine card coupled with an existing VPX host enables rapid deployment of new technology such as these faster conversion devices. With appropriate software/firmware interface design, rapid technology insertion using a FMC/VPX combination can be readily supported in future evolutions of a combat system.

The use of an FPGA-based processing infrastructure also enables the use of combination cards that feature both ADC and DAC capabilities directly coupled to the processing element (the FPGA). This approach can improve latency from input to output by an order of magnitude, an achievement of particular value within the ECM/ES domain.

There is good news on the power consumption front, too. With the increase in speed provided by these new ADC devices there is not a comparable rise in power consumption for a given conversion speed. Typically, the power consumption is around 2 W per converter. An FMC based quad channel solution will consume less than 10 W. On top of that, vendors are also likely to provide slightly lower speed dual-channel versions that boast even lower power consumption.

The utilization of the emerging high-speed, high-resolution ADC converters within the EW community will drive mission enhancement in a number of ways. It will enhance the probability of survival. It can enhance the probability of detecting SEI data. Even better, these components can now be based on industry standards, thereby reducing risk, cost, and deployment timeframes.

Robert Hoyecki is Director of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.

Rob can be reached at