Market conditions swing in favor of the custom SoC
The system-on-chip (SoC) is now a part of almost all electronic systems. As an integrated circuit (IC) that pulls together microprocessor cores, systems logic, and I/O functions, the SoC enables a wide range of product designs and is driving new markets such as the Internet of Things (IoT) and the cyber-physical systems that now underpin many industrial and automotive applications.
Traditionally, integration focused on digital functions. That is changing rapidly. According to market analyst IBS, by 2020 more than 70 percent of non-memory semiconductors will be mixed-signal designs, incorporating both digital logic and analogue processing and I/O circuitry.
The opportunities offered by SoCs – many of them provided as off-the-shelf components – are helping to drive the market for custom IC designs. Market analyst firm Semico expect the number of application-specific integrated circuit (ASIC) design starts to grow by 7.1 percent 2014, following a growth of 5.9 percent from 2013, much of it driven by mixed-signal designs. The number of first-time SoC rather than derivative product design efforts alone will rise 5.2 percent this year, according to the company.
The mixed-signal SoC makes it possible to devolve intelligence to where it is needed and enable highly efficient communication with other systems on the network, potentially extending to the wider IoT.
The key factor in these designs is not just one of cost but of size and weight. A more highly integrated solution can be packaged to fit into smaller spaces and will reduce overall weight and bulk. By bringing multiple closely linked functions onto one die, the design can benefit from power and performance improvements. These can be key factors in changing the economics of a custom IC design.
Vehicle makers, for example, are looking to SoCs to not just improve the control algorithms used in motor and guidance systems but to reduce the cost of cabling. They can encode data digitally at the point of capture and send changes in value using light, low-cost twisted-pair networks rather than the heavier, well-shielded cables needed to relay analogue signals.
Donnacha O’Riordan, director of services strategy at design house S3 Group, says, “In many of these applications, the shift to a SoC solution provides an opportunity to rethink the system architecture and take full advantage of techniques such as sensor fusion by combining digital processing and advanced mixed-signal IP.”
Cost also provides a strong reason for moving to custom SoCs. For many semiconductor products, the package that wraps around the IC is a major contributor to per-piece costs. By replacing an off-the-shelf microcontroller, mixed-signal I/O, and network devices with a single device, the systems manufacturer will save the cost of the four, five or more discrete packages on the bill of materials (BoM). Moderate volumes can easily justify the nonrecurrent engineering (NRE) expenses associated with a custom SoC.
The systems manufacturer can also save on test time and benefit from higher reliability. An SoC will reduce the total number of parts, which has the effect of increasing the mean-time between failures as well as reducing the number of infant mortalities due to PCB assembly issues. Furthermore, PCB test time will be reduced compared to designs that need to use multiple discrete devices.
A custom SoC has further key advantages when it comes to manufacturing. It can provide design security that can be difficult to achieve using off-the-shelf devices. Companies that use software alone to tune a design based around off-the-shelf parts is highly vulnerable to counterfeiting and overbuilding by rogue contract manufacturers. If criminals are able to recover the firmware from a single product, they can easily arrange for more copies to be built using the same parts. With a custom SoC, overbuilding becomes practically impossible as the contract manufacturer is able to use only the parts shipped to it by the customer.
Counterfeiting is made significantly more expensive as it involves reverse engineering the silicon, which is costly and time consuming for the criminal. They will turn to easier targets. Anti-counterfeiting, measures manufacturers can implement inside custom SoCs, make reverse engineering even more difficult. For example, it is possible to use design obfuscation techniques that disguise the operation of key components. In addition, the design team can add product keys to each device to uniquely identify it and lock the contents of on-chip memory to prevent programs or data from being read out.
A custom implementation can deliver security of supply as well. Today, there is a high risk of critical components reaching the end of their production life well before all customers have stopped using them. The use of a custom part delivers greater supply-chain control to the user and can protect against early component obsolescence.
In addition to application-driven reasons for moving to custom SoC implementations, there are strong arguments from the economics of IC manufacturing. The silicon industry is a product of learning curves. High volumes make possible detailed understanding of what drives yield – the number of fully functional chips that can be diced out of each wafer that a semiconductor fab produces.
The entire industry has benefited from the learning curves that drive Moore’s Law – the ability to double the number of functions that can be packed for the same cost onto a single piece of silicon every two years or so. There is a less obvious effect than the relentless push to finer, denser advanced nodes – the costs associated with more mature process nodes fall over time bringing them into reach for more specialized applications.
According to Gartner, foundry wafer prices for a given process node decreased over the past decade by an average of 10 percent per year. The largest falls in price tend to occur relatively early in the life cycle of a semiconductor process but over the long term, the prices on non-leading-edge wafers also fall steadily. This process reflects the increasing efficiency of wafer production as the fab’s engineers work on a process as well as the continual process of reinvention by a significant proportion of their customers as they move to later, denser processes for the benefits of higher integration.
The result is that SoC products that might have been difficult to justify economically just five years ago become not just feasible, but highly attractive alternatives to combining multiple standard products.
“The cost justifications depend on volume and system value but you can often apply the rule of 50,” O’Riordan says. If you think you can save $50 per unit from your BoM and you expect to ship 50,000 units per year, you can expect to save. But the progress of Moore’s Law and improvements in design efficiency are continuing to drive these numbers down.” Continuing investment in mature nodes by the foundries provides other compelling reasons for investigating custom SoC production. The 180 nm generation, for example, now provides integrated non-volatile flash memory, support for the high-voltage interfaces needed in industrial and automotive applications as well as ultra-low leakage current, to ensure long battery life for portable and wearable devices.
Many fabless companies and systems houses have taken advantage of these trends. Many of the startups now pursuing a fabless business model, in which they design chips that are manufactured by an independent foundry, have chosen for their products not the latest process nodes but mature processes that prove more cost-effective for their needs. Those fabless startups are able to leverage the power of customization to deliver products that offer higher performance, lower power and lower cost to their customers. To further reduce costs, many of these companies have taken advantage of the rich design and intellectual property (IP) ecosystem that has emerged to support them.
Like manufacturing, SoC implementation benefits from learning curves. ASIC and SoC design houses complete many chip-design projects each year, providing them with the tools and experience to turn projects around quickly and without errors. This greatly reduces the entry cost for any company that wants to take IP developed at the PCB and system level and apply the benefits of SoC integration.
In almost all cases the SoC will be a combination of existing IP cores and custom circuitry used to provide additional features as well as security functions. Design teams have learned to use IP cores that offer not just performance and die efficiency but maturity and robustness. These will be cores that have benefited from the learning curve through implementation by many customers.
When it comes to embedded processors, no other family of cores has had such a focus of attention as those designed by ARM. Even the EDA tools used to synthesize and lay out the circuits inside these cores are being optimized for ARM cores because of the cores’ prevalence in the market and not just for performance and area but power consumption as well.
The ARM Cortex-M processor family of 32-bit cores has proved to be successful as the basis for a wide range of microcontrollers and SoCs because it was designed for control and area efficiency. The Cortex-M0+ offers more performance with a die-area increase that is easily offset by the higher code density compared to what is possible with the 8-bit architectures once favored for low-cost mixed-signal-oriented control applications. The Cortex-M4 adds DSP instructions and support for floating-point arithmetic that can greatly enhance the performance of sensor-driven designs, particularly those that exploit concepts such as sensor fusion where inputs from multiple different signal transducers are combined into easily processed data on real-world conditions.
To help design the analogue circuitry underpinning the sensor interfaces tool support has improved significantly. Today’s software environments let engineering teams simulate different approaches long before detailed design work needs to be done. These techniques allow system-level optimizations for power, accuracy, and performance that would be impossible using off-the-shelf parts.
For example, techniques developed for advanced process nodes, such as power gating to save energy when parts of the device are idle are being rolled back to more mature processes. “When processes such as 90 nm and 65 nm were first introduced, the techniques needed for advanced power control were manually intensive. After the introduction of the 65 nm node, tool support made the process more automated and now those techniques are being applied to more mature processes,” O’Riordan says.
The result of all these trends is an environment where companies can use the experience of many different teams to create highly differentiated, well-protected product lines that take full advantage of what are now highly accessible process nodes. The custom SoC is now the smarter choice.