Model-Based Design assists DSP designers with FPGA integration

8Model-Based Design enables engineers to quickly implement and verify their algorithms on FPGAs in a workflow that can be used by engineers with or without FPGA design experience. This method also allows for easier refinements for shorter design iterations and higher levels of abstraction to facilitate the next generation of embedded FPGA devices.

Designers of Digital Signal Processing (DSP) algorithms, who are accustomed to programming processors, are turning to Field Programmable Gate Arrays (FPGAs) to gain performance advantages that come from running algorithms in dedicated hardware. However, they are often challenged by the new workflow. Unlike software development, hardware development requires engineers to think parallel, where algorithmic components execute in parallel. Other obstacles include learning the Verilog or VHDL language, mastering new IDEs from FPGA vendors, and understanding esoteric terms such as multi-cycle path and delay balancing.

Fortunately, design methodologies and tools are now available to automate the implementation of DSP algorithms on FPGAs from a system-level model. The workflow for transforming DSP algorithms into hardware consists of four steps, illustrated in Figure 1.

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Figure 1: Workflow for transforming DSP algorithms into hardware.

Market trends

Data from Xilinx and Altera show that nearly 35 percent of FPGAs are deployed in DSP applications such as wireless communications[1]. By introducing embedded FPGA devices based on ARM processors, these two vendors anticipate that more DSP applications will migrate to these integrated platforms.

Model-Based Design provides a workflow well suited to take advantage of these leading-edge silicon technologies. Automatic C and HDL code-generation technologies can greatly accelerate the development of DSP applications on these newer platforms. Automatic HDL code generation is particularly helpful for algorithm designers who are new to HDL and unfamiliar with FPGA design tools.

Because automatic HDL code generation is faster than manual hand-coding, engineers can invest some of their time savings to produce higher-quality fixed-point algorithms in the detailed design phase. This approach enables engineers to produce viable FPGA prototypes faster than with a manual workflow, as shown in Figure 2.

This illustration shows how engineers often abbreviate the detailed design phase in an attempt to begin the hardware development phase to meet development schedules. In practice, engineers will revisit the detailed-design phase during the HDL creation phase as they discover that the fixed-point algorithm is not meeting system requirements. These iterations contribute to an elongated HDL creation phase, as depicted by the long purple bar in the manual HDL coding workflow shown in Figure 2. These delays can also result in design compromises, such as glue logic or design patches.

The rest of this article describes how engineers can use Model-Based Design to implement their DSP algorithms on FPGAs more quickly than with a manual coding process.

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Figure 2: Hardware design using Model-Based Design for shorter design cycles, faster prototype development, and rapid design iterations[2
(Click graphic to zoom by 1.7x)
.]

Step 1: Modeling DSP algorithms

Investing time to design algorithms using modeling and simulation at the system level before selecting an architecture ultimately leads to better-performing systems. By working at a high level of abstraction, engineers can quickly evaluate multiple types of algorithms and architectures for specified design constraints.

For example, engineers can analyze the effect of fixed-point quantization early in the design process and optimize the word length to yield smaller and more power-efficient implementations. In the example illustrated in Figure 3, fixed-point analysis decreased the word length by as much as 8 bits.

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Figure 3: Using fixed-point analysis to identify optimal word lengths and fraction lengths for more-efficient hardware designs.
(Click graphic to zoom by 1.5x)

Step 2: Generating HDL code

Verilog and VHDL are industry-standard HDLs used to design FPGAs. The vast majority of FPGA design is done using handwritten HDL code. Recent technology enhancements provide a way to automatically generate HDL code from high-level system models. Automatic HDL code generation provides several important benefits, enabling engineers to:

·    Quickly prototype the DSP algorithm on FPGAs

·    Iterate on different algorithm design choices faster

·    Better reuse algorithmic development work

To make sure the generated HDL code meets area and speed requirements, automatic HDL code generation provides capabilities to automatically insert and distribute pipelining stages. Folding techniques (reusing multipliers) can also be used to generate more area-efficient implementations. This makes it easy to explore different hardware architectures without modifying the model.

In summary, step 1 enables engineers to explore different algorithm architectures and select the best one. With step 2, engineers can select and optimize the best hardware architecture for that DSP implementation.

Step 3: Verifying HDL code

HDL cosimulation enables engineers to reuse system models to drive stimuli into the HDL simulator and perform system-level analysis of the simulation output interactively (see Figure 4). This saves the time and effort of manually creating HDL test benches.

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Figure 4: Using HDL cosimulation to debug HDL code before committing to a hardware implementation saves time.
(Click graphic to zoom by 1.5x)

Moreover, HDL co-simulation enables engineers to have a detailed view of the digital logic as well as the system-level performance. For example, engineers can concurrently view the frequency response of a given filter in a spectrum scope and the time domain view in the digital waveform of an HDL simulator.

Step 4: Creating and verify FPGA Prototypes

Once the design has been verified via system-level simulations and HDL cosimulation, engineers can proceed with FPGA implementation. FPGA-based verification of the algorithm also known as FPGA-in-the-loop simulation increases confidence that the algorithm will work in the real world. It enables engineers to run test scenarios faster than using HDL simulation.

The test bench components of the original system model, consisting of the stimulus and analysis parts, are used to drive FPGA input stimuli and to analyze the output of the FPGA (see Figure 5). As with HDL cosimulation, the results are always available in the system model for analysis.

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Figure 5: Using FPGA-in-the-loop to verify correct system-level behavior in silicon.
(Click graphic to zoom by 1.4x)

Though slower than FPGA-in-the-loop simulation, HDL cosimulation provides more visibility into the HDL code. It is, therefore, well suited for more detailed analysis of the problem areas found during FPGA-in-the-loop simulation.

Efficiently develop FPGA prototypes

Model-Based Design helps DSP engineers to develop FPGA prototypes much faster and with a greater degree of confidence than manual HDL coding workflows using industry standard languages like Verilog and VHDL. This workflow enables engineers to continually refine their models and regenerate code for FPGA implementation, leading to much shorter design iterations. Model-Based Design also provides a higher level of abstraction that is needed to facilitate adoption of next generation of embedded FPGA devices based on ARM processors.

References

[1] Xilinx corporate fact sheet: http://files.shareholder.com/downloads/XLNX/1865202313x0x560026/71CA8916-01E0-42FA-9FA6-2CDCF9917214/Q4FY12_Factsheet.pdf

[2]Altera Corporation CY2011 Annual Report:

https://materials.proxyvote.com/Approved/021441/20120312/AR_120762/HTML2/altera-ar2011_0022.htm

[3] MathWorks Semtech User Story:

http://www.mathworks.com/company/user_stories/Semtech-Speeds-Development-of-Digital-Receiver-FPGAs-and-ASICs.html

 

Sudhir Sharma is the HDL Coder product marketing manager at MathWorks, a role he has held after being the product manager for signal processing and communications. Prior to this, he has served in key technical and management roles at Texas Instruments, Cirrus Logic, and Compaq Computer Corp. Sudhir has designed more than a dozen ASICs and authored several U.S. patents in the area of computer networks, image processing, and semiconductor memory design

Stephan van Beek is a Signal Processing and Communications Application Engineer for MathWorks, focusing on FPGA implementation. Prior to this, Stephan worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. He has also worked as a field service engineer for motion control systems at Anorad Europe BV. Stephan studied electrical engineering at the Polytechnic in Eindhoven.

Sudeepa Prakash is the HDL Verifier product marketing manager at MathWorks. Prior to this, Sudeepa was at Johnson Controls Inc. as an embedded software engineer responsible for automatic code generation of control systems. She has also worked on digital modules for RADARs using HDL Code generation with scientists at LRDE in India. Sudeepa has a Master’s degree in computer science from the University of Wisconsin- Milwaukee and a Bachelors in Electronics and Communications from Visvesvaraya Technological University.

 

MathWorks

www.mathworks.com/hdl-code-generation-verification/