New 28nm FPGAs deliver greater performance and new challenges to mil system integrators

Image processing, SIGINT, and radar designers addressing defense applications have both new performance and new hurdles ahead.

Recently the two major vendors, Xilinx and Altera, announced next-generation high-performance process-based devices. Promised for delivery in 2011, these dramatically leapfrog the features of earlier 40nm offerings. These two FPGA heavyweights are going toe-to-toe, and no matter who comes out ahead, designers of , , and systems for the and aerospace embedded market will be winners. Xilinx has long been the dominant FPGA supplier in the application space, with Altera a strong competitor. In the last several years, however, Altera has significantly increased its efforts to build on past successes in the embedded military sector, and now, with its new Stratix V GT FPGA promising high-speed serial links rated at up to 28 Gbps, they are well positioned to give Xilinx a run for its money. Xilinx’s new 28nm device, the Virtex-7, supports up to 80 serial link transceivers at rates up to 13.1 Gbps with 28 Gbps transceivers promised on future versions. Gate counts have grown substantially, too, with Stratix V offering up to 1.1 million logic elements and Virtex 7 hitting the 2 million mark.

We can expect that leading COTS board vendors such as will soon be taking advantage of these new devices, and offering next-generation versions of today’s high-performance FPGA boards such as the Virtex 5-based 720 and VPX3-450 (Figure 1).

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Figure 1: With the advent of 28nm process technology, next-generation FPGA boards are not far behind.
(Click graphic to zoom by 1.9x)

 

The always performance-hungry military market is poised to reap the benefits of new 28nm FPGAs. Compared to today’s devices the newcomers essentially deliver 2x the number of logic gates and serial links at much faster rates than were previously available on the chip vendors’ top-of-the-line FPGAs. This trend is mostly a boon for military COTS system integrators. The higher-speed serial links and greater quantity of gates will help improve computation throughput for the FFTs and other algorithms that are key to radar and SIGINT, and, to a lesser extent, image processing applications. All of these improvements are coming in packages of similar size and with roughly the same thermal management requirements as their predecessors. Even better, the price is similar, too.

Taking advantage of all of this FPGA firepower has its challenges, though. As the speed of the device’s serial links increases we start to confront the problem of data rates outstripping the theoretical limits of the popular backplanes. With connectors and trace lengths lagging behind the potential speed of the serial links, the downside can be bottlenecks. What we are likely to see is a hierarchy of link speeds. In descending order, onboard FPGA-to-FPGA links will be very high speed, FPGA-to-FMC mezzanine modules less so, off-the-board links slower still, and chassis-to-chassis links even pokier.

Another less rosy result of these great leaps in FPGA device capacity and performance will be the challenge of programming the complex new chips. Programming FPGAs has always required specialized talents and sophisticated tools, which, while constantly improving, haven’t typically improved as quickly as gate count, serial link count, and link speed have grown. But, we may now be approaching the point where FPGA programming tools will have difficulty handling the huge numbers of gates and the requisite routing. With today’s 40nm FPGAs it is not unusual for build runs to take up to five or six hours to complete. With the new 28nm devices, as gate counts and routing complexities increase, timing constraints will get much tighter.

FPGA designs require an established, defined data flow and a “timing budget” that has to be met to ensure that data flow. The larger the FPGA’s logic gate count, the farther any individual data signal must travel. And the greater distance the data signal has to travel, the harder it is to meet the design’s timing budget. The effort to optimize the routing to meet the budget can require continually modifying the FPGA layout through a sort of trial and error process to meet the budget and various signal level constraints. Unfortunately, the more constraints on a design, the harder it is for tools to complete tasks, and sometimes they just give up. Meanwhile, in an effort to meet the programming challenge, chip vendors, third parties, and universities are all hammering away at the problem.

So, while the very good news is that FPGA vendors are bringing more powerful and larger devices to market, enabling military system designers to more readily integrate systems able to perform real-time processing on the constantly increasing amounts of incoming sensor data, that old saw about being careful what you wish for is in full effect. Ensuring that we can optimally and fully exploit the new levels of performance these devices deliver is the next part of the equation.

Robert Hoyecki is Vice President of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.

Rob can be reached at info@cwcembedded.com.