Noise considerations in high-speed converter signal chains

Designing in high-speed analog signal chains can be somewhat challenging with all the noise sources to take into account. Whether it is high-speed (>10 MHz) or low-speed frequencies, the converter should really be viewed as a high-speed mixer and that all input pins, regardless of their makeup (such as analog, clock or power), can allow noise to convolve onto the output spectrum.

have a specified noise floor, which is process limited depending on what node or bias it resides in. In most cases today, high-speed ADCs are being designed in 0.18u CMOS, which means that the analog supply (AVDD) is +1.8 V. This trend continues to push the boundaries on the other surrounding/support parts that drive the analog inputs, clock and bias the converter. Because this headroom of the converter is continuously being constrained, maintaining a very low noise spectral density of -150 dBFS/Hz and lower is challenging with each new design. This is why it is paramount that the designer recognizes the importance of the surrounding noise contributions within the entire signal chain solution.

Here a focus on the most common outside noise sources and how this influences the total dynamic system performance of a high-speed signal chain will be unveiled as well as some analog and digital tricks that can be employed to further increase the signal-to-noise ratio (SNR) in your next design.

Noise Basics

First, let’s get it straight, there are a lot of noise principles, but here we are going to cover only two: noise bandwidth and the addition of noise sources.

Noise bandwidth is not the same as the typical -3dB bandwidth of an amplifier or filter cutoff point. The shape for noise takes on a different form, rectangular, which specifies the total integration of the bandwidth. Understanding this you need to make a slight adjustment in your noise calculation when considering the noise bandwidth contribution.

For a first order system, for example a 1st order lowpass filter, the noise bandwidth is 57 percent larger. For a second order system this is 22 percent larger and for a third order system it is 15.5 percent larger and so on. The designer can use the following table below as a quick reference when including noise bandwidth in the calculations:


Table 1: Noise bandwidth vs. system order.

Sources of noise come in all forms and when you add noise sources they are uncorrelated and they resolve into a smaller unit rather than a straight summation. Therefore, you can benefit from this in order to push the current boundaries limited by a single device today. The advantage, if it makes sense for your application, is that you can sum drivers/amplifiers or converters or both to improve the SNR dynamic range of the system.

Let’s look at this in brief: SNR, in dB, is a key performance metric for applications such as ultrasound and radar. The ADCs used in these systems can be affected by many external noise sources, including clock noise, power supply noise, and layout-induced digital noise coupling. As long as the square root of the sum of the squares (root-sum-square, or RSS) of non-correlated noise sources is less than the inherent quantization noise of the , output averaging can effectively lower the overall noise floor.

Systems requiring higher SNR often use digital post processors to sum the outputs of multiple ADC channels. However, the same can be done using frontend drivers, such as amplifiers, too, in the analog domain if necessary. Signals add directly, while noise from the individual ADCs or amplifiers are assumed to be uncorrelated which sums as an RSS, so summing techniques can improve the overall SNR in terms of dynamic range.

Figure 1: Basic block diagram of summing four ADC in parallel.

For example, summing the outputs of four ADCs improves the SNR by 6 dB, or 1 BIT. The input to each ADC consists of a signal term (VS) and a noise term (VN). Summing four noisy voltage sources results in a total voltage, VT, which is the linear sum of the four signal voltages plus the RSS of the four noise voltages (Figure 2).

Figure 2: Total noise equation.

Since VS1 = VS2 = VS3 = VS4, the signal has effectively been multiplied by four, while the converter noise—with equal rms values—has been multiplied by only two, thereby increasing the signal-to-noise ratio by a factor of two, or 6.02 dB. Thus, the 6.02-dB increase (delta SNR) that results from summing four like signals gives rise to one additional bit of effective resolution. Since SNR(dB) = 6.02N + 1.76, where N is the number of bits (Figure 3).

Figure 3: Effective resolution equation for multi-channel systems.

Table 2 shows the increased SNR that results from summing the outputs of multiple devices. From the standpoint of simplicity, summing four devices is an obvious choice based on area, power and packaging. Larger numbers may also be of interest in critical cases, but that would depend on other system specifications (including cost) and the amount of board space available and of course power consumption.


Table 2: Number of ADCs vs. SNR increase.

The ideal SNR for a 14-bit ADC is (6.02 X 14) + 1.76 = 86.04 dB. A typical 14bit ADC data sheet specifies an SNR of 74 dB, thus, yielding an ENOB of 12 bits (Figure 4).

Figure 4: ENOB equation.

Newer designs today continue to push down the core power of the ADCs. Making both quad and octal ADCs readily available in the marketplace, such as the AD9253, 14 bit, 125 MSps quad ADC. For multiple-ADC systems, this means easier implementation and more space-savings. Thus, by summing the outputs of four, 14-bit converters together the designer can recoup one extra bit, pushing the system-level ENOB to 13 bits or 80 dB as shown above. The same techniques can be employed for dual and quad amplifiers as well which will therefore, decrease the additive noise seen by the converter.

Figure 5: Summation SNR performance vs. frequency.

Noise contributions

Just about every circuit component has some inherent finite amount of noise, especially if it is an active device. Let’s first start with resistors. Resistors are little noisy heaters generating some finite amount of thermal noise end of story. Their contribution is little but if the designer uses high value resistors wrapped around an amplifier to drive the converter, its noise contribution can become significant relative to the desired performance. Surround that resistor with a little gain and you get even more noise.

First, let’s define the resistive noise generator. This error, Et which is represented as sqrt(4kTRΔf). Where k = 1.38 X 10E-23 W/s/K = Boltzman’s Constant , R = resistance in ohms, T = 290Kelvin, f = noise bandwidth of the system in Hertz. So, for example: a 1kohm resistor is equal to 4nVrms/Hz in a 1 Hz bandwidth. You can quickly use this unit of measure to get a brief idea on scaling all your resistive noise sources in the circuit.

Shown here is how to sum all the resistor noise and include gain to get the total output referred noise. For example, an amplifier noise model using the AD8138 amplifier is shown in Figure 6.

Figure 6: Amplifier noise model.

Notice the amplifier specifically has some voltage noise sources (En) and some current noise sources (In). These are defined as En and In respectfully and can be found in the amplifier’s datasheet specifications. Each of the resistor noise sources are also defined appropriately as well.

Going through some simple calculations you can see that the following equations can be defined and the total output referred (RTO) noise of the above amplifier circuit can be found. This is shown below:

·    Resistor Noise = 4nV/sqrt(Hz) per 1k ohm

·       En, In & BW are found in AD8138 datasheet

o    Noise Bandwidth = 1.57 * 3dB BW or NBW = 320 MHz*1.57 = 502.4 MHz

o    En = 5nV/sqrt(Hz), In = 2pA/sqrt(Hz)

o    Ei = (550/1000)*4n = 2.2nV/sqrt(Hz), Ef = (557/1000)*4n = 2.23nV/sqrt(Hz)

·    Rinput Voltage Noise = Ei*(1 + 557/605) = 4.23nV/sqrt(Hz)

·    AD8138 Voltage Noise = En*(1 + 557/605) = 9.6nV/sqrt(Hz)

·    AD8138 Current Noise = (In*557 || 605)*(1 + 557/605) = 1.11nV/sqrt(Hz)

·    Frontend Noise = sqrt((Rinput Voltage Noise)^2 + (AD8138 Votlage Noise)^2 + (AD8138 Current Noise)^2 + (Ef)^2) = sqrt((4.23n^2+9.6n^2+1.11n^2+2.23n^2)) = 10.8nV/sqrt(Hz)

·    Total Noise = sqrt(NBW)*Frontend Noise = 241.7uVrms

Note, amplifiers are different from op-amps, simply because they include resistive elements inside them. So the noise calculation is really included in the overall noise contribution given in the datasheet. This is usually found in the datasheet as RTI, or Referred To Input Noise. That way by choosing the gain in the amplifier circuit you can quickly use the RTI number and scale it as such:

RTI = 1.3nV/sqrt(Hz), Gain = 16dB, therefore, RTO = 1.3*10^(16/20) = 8.2nV/sqrt(Hz)

Using an amplifier with integrated resistors is much easier to do a noise analysis with.

Now let’s look at clock noise, or jitter. This noise affects the converter’s performance and if you have a basic understanding on how to factor this noise in, assuming it is broadband, then you can easily get a sense of the degradation due to this metric.

Simply use the broadband jitter noise in Sec (hopefully femto-seconds or below) and the analog input frequency or IF frequency of interest. We know from that the max error will occur when the clock amplitude is at its highest and assuming a sinewave input. A simple equation can be derives to get the rms voltage error. For example, a 30 MHz analog input IF and a clock jitter of 100fSec will yield a broadband voltage noise of 56.5uV or 2* π *90M*100f.

Lastly, we can explore power supply noise. What we need here is the noise of the LDO itself and its measured band. This again can usually be found in the regulator’s datasheet. For example a regulator could have a 225uV of noise over a 100 kHz BW. If this is known and the noise again is treated as white, then we can use this to get an estimate of how this might contribute to the ADC’s noise performance (SNR). However, we need to know the ADC’s power supply rejection (PSR). In most cases, it is -40 to -60dB over the first Nyquist in the analog supply domain (AVDD) so in this case let’s use -40dB in this assumption for simplicity. This gives an effective noise contribution of 7.12nV or 225u/sqrt(100k)*10^(-40/20). Keep in mind this is only for one supply domain as noted. All the supply domains need to be evaluated in the same manner and each domain may have different PSR values within the ADC, amplifier, etc.

Factoring all this noise into the signal chain design

Now that all the individual contributions have been explained let’s put an example together in order to make these principles solid and understand the overall dynamic performance of the entire signal chain. In this example, we will look at the ADL5566 amplifier driving the AD9643 ADC and separate power supplies, ADP1708 and ADP1706, biasing the amplifier and converter respectively as shown in Figure 7.

Figure 7: Example: Signal chain block diagram.

Since a lot of the upfront work had already been completed in the examples above, the next item to figure out is the ADC’s thermal noise.

On the AD9643 the analog input fullscale is 1.75Vpp differential which has a datasheet SNR of 71.7dBFS. By back-calculating the SNR equation the following thermal noise can be found:

SNR = 20*log(Fullscale (Vrms)/ Thermal Noise (Vrms)) or                 

71.7 = 20*log((1.75/2/sqrt(2))/ Thermal Noise (Vrms)) or 161uVrms

Okay, now let’s find out the noise contribution of the power supplies. We know from above in the example calculation that the AVDD contribution for the ADC’s analog supply is 7.12nVrms.

Let’s do the same for the DRVDD supply of the converter and the AVDD supply of the amplifier as well. In these two calculations we have found the PSRR of the DRVDD to be -80dB and the PSRR of the AVDD of the amplifier to be -60dB. Over the same band gives us 71.2pVrms and 1.42nVrms noise contributions respectively.

Amp AVDD = 450u/sqrt(100k)*10^(-60/20) = 1.42nV

ADC AVDD = 225u/sqrt(100k)*10^(-40/20) = 7.12nV

ADC DRVDD = 225u/sqrt(100k)*10^(-80/20) = 71.2pV

To find the total noise contribution of the supplies, simply RSS these three noise sources which gives us a total of 7.26nVrms or sqrt(7.12n^2 + 71.2p^2 + 1.42n^2).

From the amplifier example above, the ADL5566 RTO noise is 8.2nV/sqrt(Hz) with a max gain of 16dB. Next the amount of bandwidth needs to be defined. Typically an anti-aliasing filter is used between the output of the amplifier and the input of the converter. Otherwise, all the broadband noise of the amplifier will fold back in-band. Limiting this noise, it will be assumed that the bandwidth of the filter is 150 MHz, (-3 dB point). This number is used because the AD9643 is a 250 MSps ADC and has a Nquist band of Fs/2 or 125 MHz. Typically to capture the entire Nquist band of interest the AAF is designed to be a bit larger. As shown in Figure 7 a second order system or two-pole LC filter was used for the AAF implementation this will yield a noise bandwidth of 150M * 1.22 = 183 MHz. Therefore, we can calculate the noise contribution of the amplifier to be 111uVrms or 8.2nV/sqrt(183M).

Now simply RSS all the noise sources derives above using the standard SNR equation:

SNR = 20*log(((1.75/2)/sqrt(2))/sqrt(161u^2 + 111u^2 + 7.26n^2 + 56.5u^2)) = 69.66 dB

So what we have found from this is the total signal dynamic range in terms of SNR. As you begin to look at these contributions in more detail it can be easily understood on what part of the signal chain is “donating” the highest contribution. Understanding these noise sources gives insight to tradeoffs in order to achieve the best performance overall giving the associated parts chosen.

Figure 8: FFT/Noise floor difference between 1 Amp and 2 Amps summed.

Signal chain design performance

Understanding noise tradeoffs and root causes of noise within a signal chain can lead to an easier design up front. Here it has been shown, how all the devices, active and passive, interact within a signal chain in order to closely predict the SNR dynamic range performance outcome of the entire signal chain. Keep these principles in mind when doing the next signal chain design.


The author would like to acknowledge David Brown and William Nguyen for their help in the lab and measurement collection.

Graphics of my spreadsheet analysis are below to refer to or tailor for your next design. If you have further questions, connect with me on Analog Devices EngineerZone online technical support community at RReeder.

Figure 9: SNR equations/results.

Figure 10: SFDR/power equations/results with signal chain.

Analog Devices

Rob Reeder is a senior system application engineer with Analog Devices Inc. in the Industrial and Instrumentation Segment focusing on Military and Aerospace Applications. He has published numerous papers on converter interfaces, converter testing and analog signal chain design for a variety of applications. Formerly, Rob was an application engineer for the high-speed converter product line for 8 years. His prior experience also includes test development and analog design engineer for the Multi-Chip Products group at ADI designing analog signal chain modules for space, military, and high-reliability applications for 5 years. Rob received his MSEE and BSEE from Northern Illinois University in DeKalb, Ill., in 1998 and 1996 respectively. When Rob isn’t writing papers late at night or in the lab hacking up circuits, he enjoys hanging around at the gym, mixing techno music and most importantly chilling out with his two boys. Rob is a member of Analog Devices EngineerZone Online Technical Support Community.

Feel free to connect with him, RReeder, on EngineerZone.



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