OpenVPX and high-speed interconnects usher in a new era of highly scalable DSP systems

Rob explains why the OpenVPX framwork will help system designers meet the requirements of large-scale High Performance Embedded Computing (HPEC) systems.

The need for increased situational awareness via Intelligence, Surveillance, and Reconnaissance (ISR) systems continues to challenge designers of High-Performance Embedded Computing (HPEC) military DSP systems as they strive to meet size, weight, power, cooling, and cost objectives. Until now, the most advanced systems have required custom hardware and software solutions. Thanks to recent innovations, including advancements in processor performance, increased interconnect fabric speeds, and software tools, as well as the new OpenVPX/VITA 65 system interoperability framework, it’s now possible for the first time to integrate high-performance, large-scale DSP systems with open standards embedded computing hardware and software.

One of the persisting challenges facing system designers integrating these new open standards-based HPEC systems is how to handle the environmental challenges of the military space while avoiding the burdensome costs of custom hardware, software, and exotic cooling.

By applying new open architecture processors, interconnect fabrics, software APIs, and middleware, COTS vendors are now poised to enable once-unachievable HPEC in extremely rugged environments using industry-standard open architectures such as OpenVPX.

The main obstacle to using open standard architecture to address very large DSP systems has been scalability. Although it was possible to build large systems using VME, for example, unless a costly, proprietary, non-open interconnect was used, the system integrator was restricted to a low-speed VMEbus and fabric such as Ethernet, which drastically limited interconnect performance. While it’s possible to build a large DSP system today using Ethernet to connect every single module, interprocessor I/O performance would suffer.

In recent years, maturing multiprocessor software development tools, libraries, and APIs have emerged to provide military systems integrators with a new approach to HPEC. New interconnect fabrics based on industry standards such as Serial RapidIO, Gigabit Ethernet, and 10 Gigabit Ethernet now supply the I/O bandwidth and scalability needed for many HPEC systems. Using Serial RapidIO and high-speed fabric switches, designers are building high-performance embedded computers with many interconnects between processors based on standard open architectures.

The next-generation VPX (VITA 46) board architecture also addresses the backplane performance limitations of VME. By improving implementation of open standards and interoperability at the system level, OpenVPX interoperability profile definitions reduce customization, testing, cost, and risk. OpenVPX defines the VPX Systems Specification, an architecture that manages and constrains module and backplane designs. The VPX Systems Specification includes the definition of pin-outs and sets interoperability points within VPX while maintaining full compliance with the existing VPX specification. VPX, with its far greater bandwidth and support for distributed computing, is rapidly emerging as the VME of the 21st century. It promises to enable vendors such as Curtiss-Wright Controls Embedded Computing to provide the aerospace and defense market with far larger and more powerful system solutions based on SBC and signal processor engine technologies.

To meet the requirements of large-scale HPEC systems, system designers require alignment with system design goals such as those identified by the HPEC Software Initiative (, which targets:

·        Portability: Reduction in lines-of-code to change, port, or scale to a new system

·        Productivity: Reduction in overall lines-of-code

·        Performance: Computation and communication benchmarks


The integration flexibility made possible by OpenVPX promises the configuration ease long associated with VMEbus systems, enabling the simple intermixing of cards from different vendors. Coupled with the benefits of interoperability and multivendor support, the additional advantage of scalability allows a system that can grow from simple to a very large size.

Another limitation of earlier approaches to building large-scale DSP systems using standard VME and proprietary fabrics was that these cards were typically only offered in air-cooled configurations. Conduction-cooled rugged hardware for proprietary fabrics required costly, custom board designs. Now, VPX, with its support for conduction cooling and, via VITA 48, advanced cooling methods such as air and liquid flow-through cooling, enables standard COTS boards that support scalable, high-bandwidth fabrics.

Along with these advantages comes the flexibility of bringing different types of I/O directly into the fabric. Data can be brought directly into FPGAs and the actual fabric. Once the data is on the fabric, it can be sent to any processor in the system.

Curtiss-Wright Controls Embedded Computing has recently initiated a program to address HPEC requirements in rugged environments. This initiative will combine standard open architecture hardware and software components, integrated to form a flexible and scalable HPEC product family. These systems will significantly enable component reuse and facilitate rapid technology insertion. Technologies such as SBC, DSP, FPGA, A/D, and other open standards with published interfaces will form a pool of resources interconnected via industry-standard fabrics.

Open standards-based HPEC systems (Figure 1) using OpenVPX and Serial RapidIO will make possible such ISR-desired applications as unmanned ground vehicles (Figure 2) and airborne systems.

Figure 1: A 12-slot OpenVPX-based switchless cluster high-density DSP system

Figure 2: RPSAW MS-1 unmanned convoy security vehicle. Photo courtesy U.S. Army


Robert Hoyecki is Director of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.

Rob can be reached at