OpenVPX systems speed the move to all-digital RADAR
Rob describes the elements in place today for making migration to all-Digital Array RADAR a reality.
Most deployed military RADAR is made up of traditional electronically scanned phased array (ESA) RADAR technology with 100s to 10,000s of Transmit and Receive (TR) elements. These systems vary in implementation, but most cluster the TR elements, beamform, and then digitize the resultant analog signal. Digital Beamformers (DBFs) aggregate the digitized signals and then via various mathematical techniques create a final beamformed image to target computers for other various RADAR requirements.
Using new Analog-Digital converters (ADCs), high-bandwidth low-latency networks, and significant improvements to digital signal processors, it will soon be possible to complete digitization at the element level and design all-Digital Array RADARs (DARs). Military systems integrators will be challenged to scale programs from traditional systolic DBF designs to fully parallel DBFs. OpenVPX-based systems, with their novel approach to backplane interconnect, will enable system designers to migrate current ESA RADAR to DARs. Even better, OpenVPX’s flexible and scalable architecture will enable military system integrators to improve Total Cost of Ownership (TCO) today.
RADAR functions are typically used to locate, track, and identify objects. They do this by emitting radio waves and capturing the return signal by some type of sensor. This process has evolved from one where early RADARs used single emitters to RADARs employing multiple sensors in an array. These sensor arrays have two components: transmit and receive, also known as TR elements. The process of aggregating these elements together to locate, track, and identify is beamforming. In the early days of RADAR, beamforming was done entirely in analog. Now we have new technologies such as high-speed, large-bandwidth, and low-noise ADCs. These, along with high-speed, large-bandwidth, and low-latency networks and high-speed DSPs are bringing increased digitization to RADAR systems.
Implementing ESA RADAR systems on OpenVPX and using COTS boards leverages the embedded community without spending significant funds on in-house designs or other proprietary system offerings. Also, the use of COTS-based OpenVPX systems will enable system designers to change mission needs by reconfiguring data flow on new modules to achieve higher levels of digitization. Mission capability thus improves without drastic changes to the system backplane. This would be an example of capability mission upgrade by sparing.
OpenVPX distinguishes planes and user-defined pins. Planes are wafer pins routed through the backplane to other wafer pins. For example, if a backplane topology calls for one fat pipe routed to another slot, then that connection pipe is a plane. User-defined wafer pins connect through the backplane to a Rear Transition Module (RTM), and there is no slot-to-slot connection of these pins. The VPX module developer can use these user-defined pins for any purpose without worrying about interoperability with other modules. Fabric connections that are not part of plane have no connection to another slot or to the RTM. OpenVPX defines interoperability at the mechanical, module, and the backplane level.
OpenVPX-based RADAR systems require low-latency, high-bandwidth connections at the data plane and meshed and central switched designs have their corresponding advantages and disadvantages depending on what function of the RADAR is instantiated by which COTS boards. However, beamforming can benefit by data streaming. The expansion bus maps this data streaming concept to OpenVPX.
Combining OpenVPX, COTS to make DARs
One example of how an OpenVPX-based RADAR system could be integrated with COTS boards uses Curtiss-Wright Controls’ CHAMP-AV6 (Figure 1), 5xx series FMCs, HPE720, and a future Serial RapidIO (sRIO) switch all integrated in a OpenVPX chassis with the same backplane profile. The CHAMP-AV6 is an OpenVPX COTS VPX board. The CHAMP-AV6 has generous amounts of sRIO data plane bandwidth (four FP of sRIO capable of 1 GBps duplex bandwidth) and DSP functionality (four dual-core 8641 at 1 GHz or 64 GFLOPs). The HPE720 is an FMC enabled FPGA board with two Virtex-5 FPGAs. Equally, the HPE720 has similar data plane capability like the AV6, but adds an x8 Rocket I/O expansion plane connection.
One approach (Figure 2) would be to connect two HPE720s via the expansion plane to beamform in a classic systolic system. Scaling this system with multiple TR elements could be achieved by interconnecting the HPE720s sRIO to a central sRIO fabric switch. The systolic beamform is done in series where the final digital beamform of the resultant beams is handled by the Power Architecture processors connected to the HPE720s. If the processors on the HPE720 do not have enough processing capability, CHAMP-AV6s can be added to the switched fabric to increase the processing capability.
It’s also possible to configure an all-digital beamformer (Figure 3). Combining these concepts, the system integrator can mix these boards for different levels of digitization. But most important, these designs could be achieved without changing the backplane or, if clever, without moving the boards. These changes could be made entirely by a change in software in the processors and VHDL code in the FPGAs.
The evolution from ESA RADAR to DAR RADAR is made easier using COTS boards and open standard systems. OpenVPX based systems with their unique high-bandwidth, flexible backplane interconnect will allow system designers to provide significant flexibility to migrate current ESA RADAR to DARs.
Robert Hoyecki is Vice President of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on signal process products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.
Rob can be reached at firstname.lastname@example.org.