Optimizing performance, power, and area in processors to meet increasing demands

Mobile device, set-top box, base station, and server-class all need to increase performance, reduce power draw, reduce turnaround time, and reduce area to keep costs down. Previously, to optimize on-chip IP cores, SoC designers needed individual design kits for different processing elements, and there were no optimization kits for DSPs. However, designers can now get increased performance and reductions in area, power, and turnaround time for all three processor types – CPUs and GPUs as well as DSPs – in a single kit.

Instead of needing separate design kits from individual processor makers, ’ DesignWare High Performance Core (HPC) Design Kit contains a suite of high-speed and high-density standard cell libraries and memory instances that can improve implementation in 28 nm processors by improving Performance, Power, and Area (PPA) – processors can be optimized to run faster, preserve power, and reduce chip size.

Synopsys was influenced to develop the kit when they noticed commonalities in the IP cores of CPUs, GPUs, and DSPs, but there wasn’t a single source for each. By combining the memory and logic libraries of all three into a single kit, they found that they had created an optimized group of best practices in a single set of IP that enables customers to solve the problems of all three processor types with faster results and better overall performance and optimization. Customers were also able to put more on a single die, creating more value.

The design kit is an add-on to the Duet Package of Embedded Memories and Logic Libraries, and includes more than 125 new standard cells and memories that are especially tuned for speed and density requirements of advanced CPU, GPU, and cores. One challenge Synopsys cited was getting the right set of additional cells and memories in the kit, as brute force with all possible cells and memories would slow the tool down. The balance was achieved by working with a large variety of processors from leading customers and processor IP providers such as Imagination Technologies, CEVA, and VeriSilicon.

Designing processors using the kit demonstrated up to a 10 percent increase in performance, a 10 percent decrease in area, a 25 percent lower power draw, and a 30 percent reduction in turnaround time over the standard Synopsys Duet Package. In a case study on the Imagination PowerVR Series6 GPU in a mobile device, average area was reduced by 10 percent, leakage power by 20 percent, and dynamic power by 25 percent. Savings in area reduces cost, leakage power reduction allows for more device standby time, and dynamic power reduction increases talk time in mobile phones.

Though all four improvement areas are valuable to designers, a 25 percent power reduction is, without a doubt, the biggest achievement, says Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys.

The power reduction stands out especially because many 28 nm chips being developed today are very power conscious, added Prasad Saggurti, Product Marketing Manager, Embedded Memory IP, Synopsys.

During development, a leading provider of CPUs for green servers achieved significant dynamic power savings. This directly benefitted their customers by allowing them to reduce the number of costly generators needed to keep their servers running during power outages. As servers are constantly running, the dynamic power reduction on processors can be a significant factor, especially for customers striving to maintain a green identity. Dynamic and leakage power savings – in addition to die area reductions – are achieved through area-optimized and multi-bit flip-flops and an ultra-high-density two-port SRAM.

“In SoC design, up to half the development time is spent trying to get the last five percent of targeted area or performance improvement,” says Brock. “With the DesignWare HPC Design Kit, designers can significantly shorten the schedule.”



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