Articles
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FPGA or GPU? - The evolution continues
A GE Intelligent Platforms perspective on embedded military electronics trends
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FMCs provide versatility and modularity across multiple platforms
The VITA 57 specification defining the FPGA Mezzanine Card (FMC) has been adopted since 2008. Today FMCs are commonly used in architectures from VPX to CompactPCI to MicroTCA and more. The versatility of the mezzanine approach allows a broad swath of acceptance in various applications.
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Can your PCB handle the speed?
The JESD204B high-speed data converter I/O standard provides for serial interface bit rates of up to 12.5 Gbps. Many system designers are embracing this “upgrade” to the digital interface. Its faster serial interface allows them to use fewer high-speed serial transceivers on their FPGA or ASIC. This reduction in the number of I/O traces enables smaller packages, smaller PCBs, and smaller overall product form factors. However, designing a reliable physical interconnect for data rates exceeding 5 Gbps may involve additional effort. As the speed increases, the transmission distance needs to be accounted for and additional channel modeling may be necessary, possibly involving a 3D field solver to ensure signal integrity.
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Market conditions swing in favor of the custom SoC
The system-on-chip (SoC) is now a part of almost all electronic systems. As an integrated circuit (IC) that pulls together microprocessor cores, systems logic, and I/O functions, the SoC enables a wide range of product designs and is driving new markets such as the Internet of Things (IoT) and the cyber-physical systems that now underpin many industrial and automotive applications.
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OpenCL and the future of FPGA and DSP development
DSPs and FPGAs have a reputation of being difficult to develop for, but the OpenCL language aims to improve software development.
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Three ways to improve PCB design productivity and predictability with hierarchical interface-aware design capability
System designers are increasingly relying on standards-based interfaces to help them meet market demands for products that are faster, boast more bandwidth, and consume less power. Design authoring has traditionally involved working with busses or bundles, with a single-level hierarchical definition of a group of signals. This process, however, doesn’t result in a fast or easy way to connect interfaces. This article examines three ways in which a hierarchical interface-aware design capability can improve PCB design productivity and predictability.
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Challenges in migrating to an LCD-based design
With industrial displays migrating to LCD designs with more user-friendly interfaces, Varadarajan weighs the costs and benefits of various architectural options.
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DSP capabilities of SoC FPGAs address emerging small cell requirements
The insatiable demand for increased communication bandwidth is driving the development of new wireless architectures and the deployment of a wide variety of new wireless infrastructure devices. Of the two key approaches – a centralized homogeneou...
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Functional and performance verification of SoC interconnects
Verifying interconnect Intellectual Property (IP) – the "glue" that holds together the cores and IP blocks in a System-on-Chip (SoC) – has become more complicated with advanced SoCs, which require special interconnect IP to perform the on-chip communication function. As a result, functional and performance verification of these SoC interconnects has taken on a new level of complexity. Tools have been developed to simplify verification while providing design engineers the ability to find and fix interconnect problems much earlier in the design cycle.
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Managing SoC complexity with scenario model verification
Graph-based scenario models assist engineers with project management, thorough verification, and other aspects of complex SoC development.
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EDA and the cloud
The effect of the cloud can be seen everywhere, in just about every industry. I had the opportunity to talk with Larry Drenan, Services Group Director with Cadence Design Systems, about the current state of EDA as well as trends and thoughts on EDA relative to the cloud.
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Reducing bugs in hardware design with EDA and formal verification technology
Complex SoCs are often behind schedule or require re-spins due to bugs not caught by verification. In order to meet hardware design challenges, and improve quality and efficiency, designers can integrate formal verification technology into the design c...
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New electronic warfare architectures based on tight coupling of FPGA and CPU processing
Electronic Warfare (EW) system designers are taking advantage of the performance leaps in commercial technology, driven by high-volume commercial markets such as telecommunications and cloud computing. These components such as FPGAs combine speed, high connectivity, and low power consumption for signal-processing intensive EW platforms such as fighter aircraft and Unmanned Aerial Vehicles (UAVs).
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Software development tools as force multipliers
Situational awareness often requires data center processing speeds in the smallest possible package. The sensors that feed signal and image processing systems siphon up masses of data, which processors must then reduce to useful information within tactical timelines.
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MIL-STD-1553 IP cores challenge traditional IC implementation
Forty years since its release, MIL-STD-1553 is evolving from traditional Integrated Circuits (ICs) to Intellectual Property (IP) cores integrated with Field Programmable Gate Arrays (FPGAs). The advantages of IP core implementation include cost reduction, the ability to upgrade and adapt a design over time, a smaller size footprint, and improved sourcing. Designers choosing IP cores must consider validation testing, code size, FPGA support, and compatibility with legacy software.
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Embedded Tech Trends in review
Editorial Director Jerry Gipper reviews Embedded Tech Trends 2014
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Embedded signal processing enables advanced radars and EW systems with low latency
Modern radar and electronic warfare designs rely heavily on embedded computing systems that leverage high-speed commercial processors and FPGAs to find every target or signal and enable the warfighter to respond in real time. Meanwhile, signal processing system designers are cutting costs by using parallel compute platforms such as OpenCL that work across multiple chip platforms.
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Common EW and radar systems for emerging military missions
Due to shrinking Department of Defense (DoD) budgets and ever-decreasing platform size, the need to use common apertures and sensor chain elements for Electronic Warfare (EW) and radar systems is becoming a necessity. System developers must use common elements from Radio Frequency (RF) to processing to build such systems. The linchpin of these types of sensor-based systems is the I/O interface between the RF and processing elements. FPGAs have traditionally been used as this I/O interface, but now they are serving as an integral part of the processing subsystem on common EW radar systems.
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Latest 40 Gbps SBCs drive new class of HPEC-Lite systems for ISR applications
The embedded defense and aerospace industry has recently seen the emergence of new embedded system elements that support 40 Gbps fabrics. These higher bandwidth hardware solutions include Single Board Computers (SBCs), DSP engines, GPGPUs, FPGA engines, network switches, and Gen3 OpenVPX backplanes.
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Digital channelizer implemented on COTS FPGA board: A flexible solution for military signal processing
One of the major challenges of modern military Digital Signal Processing (DSP) is dealing with the ever-widening bandwidth of digitized signals. Until fairly recently, analog-to-digital converters (A/D converters) were limited to only hundreds of MHz, so anything beyond that had to be dealt with using traditional RF/analog methodologies. Now that A/D converters are available in the GHz range, much wider band processing is moving to the digital domain.
John McHale, Editorial Director
