Power consumption as the competitive advantage
PL: Actel‚Äôs strategy has Design for Energy Efficiency written all over it. How did you arrive at that as a core strategy for the company, and how is it changing your business?
JE: I guess the real question is why a company wouldn‚Äôt arrive at energy efficiency as a core strategy. The industry is ripe with discussion of "green design" and industry leaders are called upon every day to act as socially responsible citizens.
Power matters. With the world‚Äôs increasing use of electronic devices, Actel has the oppor-tunity to play a major role in resolving the world‚Äôs global warming problems with further technological change.
We‚Äôre changing FPGAs from "power hogs" into "power savers." We‚Äôve designed non-volatile, reprogrammable flash-based devices offering 200 times less static power and more than 10 times the battery life than competitive SRAM-based programmablelogic solutions.
We are in the business of enabling designers to save power - from low-power FPGAsand power-efficient programmable system chips to power-optimized tools and power-smart IP.
PL: A good example is the IGLOO. What makes the IGLOO architecturea low power solution?
JE: There are three main points of interest in IGLOO.
The differentiating factor for the majority of our product line is the use of a true flash-based architecture. True nonvolatile flash-based FPGAs contain a nonvolatile FPGA array, and do not suffer from the leakage current issues associated with SRAM-based solutions.
Secondly, we felt it paramount that we select a foundry partner with a proven low-power flash process technology. We chose UMC‚Äôs leading-edge 0.13-micron low-power and e-Flash processes. Combined with IGLOO‚Äôs power mode options and Flash*Freeze technology, UMC‚Äôs processes enable power consumption as low as 5 microwatts.
Finally, the IGLOO family has several power modes to optimize power con-sumption - the Flash*Freeze mode, a low-power active mode, and a sleep mode. While in Flash*Freeze mode, the device conserves power while maintaining FPGA content. Device I/Os are tri-stated and SRAM and register content is maintained, but not clocked. Further, the Flash*Freeze pin enables designers to quickly and easily enter or exit the Flash*Freeze mode within 1 microsecond. Alternatively, the low-power active mode allows the IGLOO device to directly control when the system goes into low-power mode. While in the low-power active mode, the FPGA core, clocks, and all I/O are functional.
PL: What have you done to aid designers in power consumption analysis?
JE: The Libero 8.1 IDE has specific fea-tures to further optimize FPGA designs for low power.
The Libero IDE enables creation of realistic power profiles based on design parameters or metrics. An example is the percent of time the FPGA will be in a combination of custom or functional modes, such as Active, Standby, or Flash*Freeze. The tool then displays a realistic and accurate report of power consumption based on the true power profile of the target FPGA.
The design analysis data is then utilized to engage in power-driven layout. Use of this tool enables users to quickly realize dynamic power savings through the reduction of the capacitive loading of the nets. While average IGLOO power consumption is reduced by 13 percent, some designs can realize a 30 percent reduction in power consumption.
PL: Where do you see processor cores in FPGAs headed?
JE: We see real value there and have several cores - CoreABC, Core8051, Core8051s, and CoreMP7, as well as the FPGA-optimized ARM Cortex-M1 and the Leon3 SPARC processor.
These offerings bring the flexibility, fast time to market, and low implementation cost of FPGAs to users who can‚Äôt justify the expense of ASICs for their application. We‚Äôll continue to explore processor core technologies with more choices, better tools, and improved power optimization.
PL: I see you‚Äôre betting on MicroTCA specifically - why?
JE: We‚Äôre really interested in system management. At the high end, there are standards-based and proprietary solutions for telecommunications such as AdvancedTCA and MicroTCA. At the low end embedded applications need low cost, less complex solutions. We‚Äôre doing both.
Our mixed-signal Fusion Programmable System Chip (PSC) can perform system manage-ment functions, including power and thermal management, data logging, and system diagnostics, within high-end and low-end electronic systems. And it‚Äôs all in a single chip, with a cost and space savings of 50 percent or greater relative to current implementations while also improving reliability.
PL: How can designers get an advantage in their next FPGA-based design?
JE: Nearly every vendor claims low-power leadership. Ignore the claims and check the datasheets - static power, dynamic power, inrush, configuration power, and low-power modes.
Comparing one-million gate devices, for example, SRAM-based FPGAs marketed as the "lowest power FPGAs" state static power consumption between 40 milliwatts and 150 milliwatts, which is 800 to 3000 times higher than Actel‚Äôs 0.05 milliwatt flash-based IGLOO device. Similarly, when comparing "zero power" CPLD solutions against IGLOO, these devices consume 10 times more static power.
Then look at tools to optimize power. How does the development environment like Libero help the designer? What power-smart IP, like FPGA-optimized 32-bit ARM processors, is available? Tools are just as important as architecture.
PL: What‚Äôs next for the FPGA industry?
JE: Today, FPGAs are capable of handling so much more within a design - whether it be the interfacing and control within a smart phone or in a system-critical automotive or medical application. FPGAs are expanding into so many different applications that can leverage their flexibility, low power, and low cost.
Looking ahead, I believe a continued focus on power reduction will drive even more applications. There continues to be tremendous demand for low-power programmable solutions at lower densities to handle the control and bridging functions in portable designs. We‚Äôre now hitting the $1 price point with these solutions, particularly for price-sensitive consumer portable applications. The technology will just continue to improve.
John East is President and CEO of Actel Corporation, with nearly 40 years experience in the semiconductor industry. Prior to joining Actel in 1988, East held positions with AMD, Raytheon Semiconductor, and Fairchild Semiconductor. He has a bachelor‚Äôs of science degree in electrical engineering and a master‚Äôs degree in business administration from the University of California, Berkeley.