SIGINT in the real world presents nuances
We’ve heard that FPGAs can do signal processing algorithms. But what about the rest of the problem: controlling analog-to-digital converters, compensating for effects of voltage and temperature, and more? Here, FPGAs get serious.
The growing use of FPGAs in SIGINT applications is enabling a significant increase in the capability of defense systems. With a wider variety of threats than ever before, the desire to monitor more of the frequency spectrum necessitates a high performance front-end processing engine. A SIGINT system that needs to monitor VHF (30-300 MHz), UHF (300-1000 MHz) communications and navigational aids, through to radar and satellite communications in the L band (1-2 GHz) frequencies, requires an analog bandwidth of 2 GHz for complete and instantaneous coverage.
Since there are a wide range of frequencies and consequently a wider range of signal modulation schemes, the processing system needs to have significant I/O bandwidth to receive the data as well as the computing performance to implement real time demodulation and analysis algorithms. Typical algorithms include Digital Down conversion, ffts, filtering, and I/Q demodulation.
DSPs short on two counts
While many of the algorithms used are familiar, it is the bandwidth of the input data that makes the implementation much more challenging. As an example, taking a simple 10 tap FIR filter and using this with a high end ADC, such as a 3 GSps part, the computing performance required is 30 GMACps. While this significantly exceeds the performance of high end DSP processors that offer around 1 GMACps, it is a fraction of the performance offered by high end FPGAs that are capable of up to 350 GMACps. This means that FPGAs have horsepower to spare to carry out additional tasks which will be required by typical applications.
Not only are the performance capabilities of DSPs under-powered for high data rate processing, but the I/O bandwidth to move these high speed data streams is unavailable. While there could be a data stream of 3 GBps from an ADC, DSPs typically provide bandwidth of 1 GBps. Clearly DSPs are not capable of handling this rate of data ingress for a single data channel. This problem is exacerbated considering antenna arrays and techniques such as beamforming are common approaches to improve the SNR of received signals.
FPGAs can tackle the problem in a much smaller space. Figure 1 shows a 6U CompactPCI card with 4 daughtercards, providing a total of 8 channels that can each capture 3 GSps at 8-bits (aggregate of 24 Gbps) into 5 FPGAs that can deliver up to 1 TeraMAC/sec of processing performance. The equivalent implementation using DSP processors would require at least a full 42" rack.
More control over digitization
In addition to the I/O and processing power that FPGAs provide, they bring further benefits to front-end processing applications by affording the user a finer level of control over the digitization process. FPGAs can directly control and manipulate the interface signals of ADCs and supporting peripherals such as clock synthesizers and clock path selection. Coupling high-speed data converters with FPGAs allows direct RF sampling, enabling digital manipulation of data and hence reducing complex analog RF circuitry for tuning and demodulation. Performing these functions in the digital domain rather than analog reduces sensitivity to environmental noise and improves the repeatability of processed results.
For example, incoming SIGINT data from antenna arrays must be captured with virtually no phase skew between channels. The challenge is ensuring two ADCs are accurately synchronized in order that the samples on each analog input are coincident in time. Channel synchronization is similarly critical when capturing I/Q signals, where the SNR will be degraded if the data from the two channels is misaligned resulting in reduced receiver performance and sensitivity.
A lot goes into synchronicity
Figure 2 is a functional diagram of the daughtercard module (with four shown in Figure 1) with two National Semiconductor ADC083000 3 GSps ADCs connected directly to a Xilinx Virtex-4 FPGA. The key to synchronizing the ADCs is deasserting the device reset signal.
There are many parameters that need to be considered to ensure synchronicity of the channels, particularly when having to deal with the real world differences of time of arrival of the reset signals. In this specific implementation, the key factors that had to be considered in the analysis were:
- Skew between clock inputs of the two ADCs
- Skew between FPGA reference clock and ADC clocks
- Reference clock delay through FPGA
- Skew between the two ADC reset signals include FPGA clock to out skew
- Relative jitter of reference FPGA clock to ADC clocks
- Relative jitter between ADC clocks
- Setup and hold of reset signal
Although the FPGA is used for handling the timing of the reset, some of these parameters are out of the control of the application developer (namely, items 1, 5, 6, and 7) and so need to be characterized in order to be managed. Fortunately, the flexibility of the FPGA means it can be used to run a dynamically configurable measurement application that measures the effect of the uncontrollable parameters. Using such an application, the valid window for the reset signal was measured as 306 ps, froma total period of 666 ps (assuming a 1.5 GHz clock that is usedfor 3 GSps data capture).
The critical element to maximize the reliability of channel syn-chronization is to deassert the reset signal in the middle of this data valid window. This shifting of the reset edge is achieved using the digital clock managers (DCMs) of the FPGA, which enable fine-tuning of the clock phase within the FPGA. The two reset signals to the ADCs are transmitted from the FPGA via flip-flops so when the phase of the FPGA clock is changed, the phase relationship between the reset signal and the ADC clocks is also changed (the ADCs are clocked directly from the clock synthesizer and are therefore independent of the FPGA). This technique enables the phase of the reset signal in relation to the ADC clocks to be changed in increments of 10.4 ps when sampling at 3 GSps.
Compensating for environmental variables
At this stage it seems a straightforward task to run the measurement design, find the center of the data valid window, and pre-configure the phase of the DCM to align the reset signal at that location. Unfortunately, environmental parameters affect skew and jitter performance.
Testing showed that the phase of the valid window for the reset signal (relative to the ADC clocks) changed with temperature. A second order non-linear relationship was found between the phase setting and the frequency and temperature values, which also varied depending on the FPGA device in use. The resultant formula for a Virtex-4 SX55 device is:
Phase(SX55) = round(mod(1.5479e-006*f*f - 0.00045165*f*t
- 0.24071*f - 0.0033431*t*t + 0.27627*t + 348,256))
Where: t is the temperature in ¬∫C
f is the clock frequency of the ADCs in MHz
This result greatly simplifies the system design as the phase set-ting can be computed based on two easily known variables. The alternative is to implement a calibration circuit in the FPGA and provide synchronized analog inputs on every startup, a more error prone technique.
This application would require several hundred DSPs to implement, not to mention the need for a PLD to interface between the ADCs and processors, illustrating why FPGAs have become the first choice technology for front-end sensor processing. Not only do FPGAs provide computational prowess that reduce system SWaP by orders of magnitude, they have the I/O bandwidth and flexibility needed to implement the latest and most complex sensor interfaces.