SRIO reaches a crossroads in Intel-based DSP designs

For many years PowerPC/Power Architecture processors have been the CPU of choice for embedded military DSP applications. As a result, (SRIO), which is integrated with PowerPC processors, became established as the preferred serial communications fabric. () defines SRIO support for designers integrating high-performance radar, imaging, and signal intelligence applications. However, no practical way of using Intel CPUs in SRIO-based systems has been available. This situation has changed with two recent introductions. These are the Intel’s 2nd generation Core i7 processor and a complementary PCIe-to-SRIO bridge product from IDT. These products effectively change the landscape for developers, enabling for the first time the development of superior Intel-based .

Prior to the latest generation of Core i7 there was no real support for SRIO on Intel platforms. The gap in support critically limited the use of Intel architecture processors in DSP multiprocessor systems. Multiprocessor Intel systems could be built using InfiniBand, which, though popular in the cluster computing world, is not embraced in military applications. Using Gigabit Ethernet (GbE) or 10 GbE is another option, but SRIO, especially the latest Gen2 SRIO, offers significant advantages for DSP designs over GbE.

Microprocessor engineers designed SRIO to solve inter-processor communication. With SRIO, packet delivery is guaranteed by hardware. When an SRIO packet is transmitted, the hardware delivers it to the destination without the risk of it being dropped by a switch. By contrast, Ethernet, designed to accommodate networks spanning great distances, does not guarantee packet delivery. To ensure that data arrives safely at its destination, Ethernet verifies the fate of each packet, which adds significant overhead.

New generation silicon includes offload engines that reduce host CPU overhead, but it’s apparent from the size and power of these devices that the complexity of the protocol is demanding. Speed-wise, the new generation of Gen2 SRIO switches operates at 20 Gbps signaling, which is approximately twice that of 10 GbE when you remove header information and look at the actual payload data.

Bandwidth between processors is a key consideration in DSP systems, equally important as the performance of the processors themselves. That’s because for certain classes of algorithms it’s not the speed of the individual processors that is the limiting factor, but rather the speed at which processors communicate that dictates system performance. Computing power is important, but without fast interconnects to the other processors the overall DSP system won’t be effective, which makes the choice of fabric critical.

IDT’s PCI Express (PCIe) Gen2 to SRIO Gen2 bridge lets system designers equip Intel processors with an SRIO interface. Supporting 5 Gbps PCIe2 and SRIO2 interfaces, the bridge provides 60 percent faster performance than current 3.125 Gbps SRIO implementations. The IDT bridge’s small size and low power is good news for SWaP-constrained . Designers may use one or more bridges with a high-performance processor to scale the system bandwidth as needed. IDT’s bridge is much smaller and lower power than today’s GbE alternatives, yet 2x faster.

Based on inputs from a variety of markets, including Curtiss-Wright’s military system usage, IDT’s bridge supports multiple data transfer modes, including memory-mapped transfers and SRIO messaging. SRIO bridges implemented in typically omit SRIO messaging, a feature that maps to higher level middleware APIs such as MPI. Another plus offered by the IDT silicon is the inclusion of DMA engines that offload the host processor. Intel processors typically don’t have DMA engines on-chip, but depend instead on the peripheral chip to move data. Without a DMA engine, moving data can require a large amount of the host processor’s attention, with the result that a processor might have one of its cores largely consumed by moving data.

Another advantage of SRIO for space-constrained military systems is the ability to support all topologies including either distributed switch or centralized switch architectures. Distributed switch systems (an example is VITA 65 BPK6-CEN05-11.2.5-n) make use of the local SRIO switch and thus avoid the need for a separate switch card, saving one or more slots. For example, if the system were using a 1/2-ATR Short enclosure (four 1-inch slots), this capability saves 25 percent of the volume. For large systems, centralized switch architectures are often preferred, and SRIO is equally adept at this approach. The leading vendors all offer SRIO switch solutions.

has incorporated the IDT bridge on its new generation dual 2nd Generation Core i7-based CHAMP-AV8 6U OpenVPX , shown in Figure 1. Each board employs four bridge chips, providing two interfaces to each CPU with each interface significantly faster than the bandwidth available from a 10 GbE interface. The complementary VPX6-1956 SBC also features the bridge.

21
Figure 1: Two interfaces to each CPU are found on the new dual 2nd Generation Core i7-based OpenVPX engine from Curtiss-Wright Controls Embedded Computing, the CHAMP-AV8.
(Click graphic to zoom by 1.9x)

Robert Hoyecki is Vice President of Advanced Multi-Computing at Curtiss-Wright Controls Embedded Computing. Rob has 15 years of experience in embedded computing with a focus on products. He has held numerous leadership positions such as application engineering manager and product marketing manager. Rob earned a Bachelor’s of Science degree in Electrical Engineering Technology from Rochester Institute of Technology.

Rob can be reached at info@cwcembedded.com.