The drive to lower power

Christian explains why the demand for portable, lower- electronics is growing and describes applications where have a role today.

As process technology continues to improve, device sizes shrink, and designers pack more onto silicon real estate, FPGAs increasingly find themselves the center of attention. differentiation as measured by flexibility and time to market is finding new applications and responsibilities.

The shift toward portability and power-conscious electronics has led to the demand for low-power components of every variety, and now that includes FPGAs. Today power is a more important design consideration than performance. For some vendors this has meant offering incrementally lower-power devices, with next-generation devices being 60 percent lower power than previous generations.

The low-power trend is taking root in a variety of applications:

n  In medical devices, where there is a clamoring for portable medical equipment for quick and easy diagnosis.

n  In displays, which are being incorporated into innumerable systems.

n  In industrial equipment, where motor control design is seen as a key way to improve overall energy efficiency of products, and ultimately, of the world.

 

Low-power applications represent a new role for FPGAs. Designers have traditionally relied on ASICs, not FPGAs, to meet their low-power constraints. But hardwired ASICs – with longer time-to-market, rising non-recurring engineering charges (NREs), and a lack of flexibility to address changing standards and late-stage design modifications – are riskier and often impractical for applications with short product-life cycles or evolving standards.

Similarly, Complex Programmable Logic Devices (CPLDs), used in some low-power applications, are losing their effectiveness due to relatively high costs and the increased demand for high-end features and extra logic. CPLDs do not offer the level of integration, flexibility, or sophistication required for most of today’s applications.

Designers are finding that a low-power, reprogrammable solution is required to adapt to evolving standards, speed time to market, offer product with multiple personalities, and deliver the footprint and power consumption that cutting-edge electronics designs require.

The power-miserly FPGA

Not all programmable logic is well suited to address low-power needs. In fact, some of today’s “low-power” FPGAs draw upwards of 30 mA, which is often an order of magnitude or two higher than typical power-sensitive, battery-operated applications can tolerate. SRAM-based devices experience well-documented inrush and boot-up configuration power spikes during system initialization that can drain a battery quickly.

But single-chip, flash-based devices do not require an external configuration device (for example, a boot prom or microcontroller) to support device programming at every power-up cycle. And the live-at-power-up feature eliminates the need for an external device to assist in system boot up. Removing the additional parts required by SRAM-based FPGAs not only reduces board space and system power consumption, but also increases reliability, simplifies inventory management, and lowers total system costs by as much as 70 percent compared with similar SRAM-based FPGA solutions.

Once the FPGA is on and configured, power consumption takes two basic forms – static and dynamic. Static power consumption is the current drawn by an FPGA when it is powered up, configured, and doing nothing. Dynamic power is consumed when devices are actively working. Until recently (see Figure 1), dynamic power was the dominant source of power consumption. Once helping to manage the dynamic power problem, device supply voltages (Vcc) had scaled downward with process shrinks and subsequent lower system voltages, but the days of continued scaling are coming to a close.

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Figure 1:   Traditionally, dynamic power has been the dominant source of power consumption. Device supply voltages (Vcc) have scaled downward with process shrinks and the resulting lower system voltages, but continued scaling downward cannot be ongoing.

 

Compounding the issue, each process node shrink means additional static power consumption for transistor-heavy SRAM-based FPGAs. This is due to worsening problems like quantum tunneling and sub-threshold leakage, which create real challenges for devices targeted to power-conscious applications. And, with leakage worsening, static power has begun to dominate the power consumption equation as the biggest concern.

The SRAM cell structure incurs substantial leakage and requires power-consuming configuration memory. In sharp contrast, flash-based cells have no leakage path and thus have 1,000 times lower leakage per cell than SRAM.

Alternative approaches

To address some of these power concerns, several suppliers of SRAM-based FPGAs claim to offer “single-chip, flash-based” solutions. These “hybrid” solutions are merely combinations of flash memory components with the underlying SRAM FPGA technology – integrated with the FPGA die into a single package, or stacked, or placed side-by-side. Unfortunately, the FPGA array is still volatile and is subject to the power drawbacks associated with these types of devices. With these solutions, the embedded flash memory blocks control only the initial configuration of the devices during power-up.

Certainly, both the Silicon-in-Package (SIP) and the Multichip Package (MCP) hybrid approaches overcome some of the limitations of traditional SRAM-based solutions with a smaller footprint, a minor reduction in power consumption, and small advances in power-up time and security. But these are only incremental improvements over their pure SRAM-based peers.

True nonvolatility

True nonvolatile FPGAs are those that contain a nonvolatile FPGA array, reducing power consumption, improving response times, and delivering unparalleled reliability and security. Because true nonvolatile flash-based FPGAs don’t use millions of power-hungry SRAM configuration bit cells, they have significantly lower static power than SRAM-based solutions, making them ideal for power-sensitive applications. In fact, the many flavors of flash-based, low-cost FPGAs include devices that have been optimized for power, speed, and I/O, some of the fundamental design requirements for power- and cost-sensitive design.

Low-power FPGAs at work

Portable medical equipment made big news at the 2008 Beijing Olympics when companies, such as GE, were test-driving portable MRIs and other imaging and diagnostic tools at the Games. FPGAs are playing a big part, allowing developers to program various features, design for differing geographical standards, and imbue the devices with multiple personalities, while at the same time keeping power as well as design costs low.

This trend towards miniaturization and portability for home, clinical, and imaging medical devices presents a significant opportunity for medical equipment designers to use FPGAs in developing efficient and flexible designs.

Medical devices have high-reliability requirements, demand multifunctionality (integrated capabilities), and require and transmission capabilities. Yes these devices must consume the lowest amount of power. In the most basic form, portable medical devices are all battery-operated, microcontrolled handheld devices that take and analyze measurements using the various bio-sensors a patient’s treatment plan needs.

Home-based and consumer medical devices – digital blood pressure meters, blood gas meters, and blood glucose meters –have been traditionally used for testing and monitoring. Today, medical devices are expected to do much more than just test and monitor. Some now log and analyze data and communicate accurate results to the health provider. Blood pressure meters benefit from a more extensive data-logging feature as well as communication ports for real-time information sharing with the health provider. Insulin meters are now equipped with communication ports (IR/) to transfer real-time measurement to the PC or to the insulin pump to effectively treat the disease.

In Figure 2 the shaded functional blocks represent some possible functions that can be implemented in FPGA devices. These functions can be either individually addressed as needed by smaller low-power reprogrammable FPGA devices or can be integrated into larger FPGA devices. These ultra-low-power FPGA families offer gate capacity from 15 k gates up to 3 million gates.

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Figure 2: Gate capacity ranging from 15 k  up to 3 million  is available from ultra-low-power FPGA families.
(Click graphic to zoom by 1.3x)

 

Pressure to reduce health care costs is butting into the demand for more portable devices, which, when deployed in the home, can save the system money. But these devices need to be low power, flexible, and cost-effective for wide deployment.

Display dynamic

Let’s look at another application that is increasingly leaning on programmable logic to ensure flexibility and time to market speed: Displays.

Lower costs and ease of mass manufacturing have increased LCD panel demand in medical markets. When creating these devices to meet consumer demands, designers select LCD panels based on critical factors, such as size, resolution, reliability, power consumption, and product life cycle. As newer displays with enhanced capabilities and features are continuously launched, designers face challenges in keeping up with technology by redesigning the display controller and need solutions enabling them to incorporate the latest technology with minimal cost and effort.

In portable devices, LCDs can consume up to 50 percent of the application’s power budget, escalating the need for a power-efficient solution. Power-aware attention to the design does not rule out the use of FPGAs, which often are seen as power inefficient choices. Careful design considerations in managing power using FPGAs as a complex LCD controller, for example, can reduce power (see Figure 3).

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Figure 3: Taking on a complex LCD controller role, FPGAs can be a power-efficient option.
(Click graphic to zoom by 1.7x)

 

Some FPGAs offer low-power advantages, down to 5 mW, while retaining the contents of the system memory and data registers. As a result, the FPGA approach can enable both the LCD panel and the controller to function in a power-saving mode with the LCD data and backlight disabled, achieving significant battery savings.

Motor control

New designs for AC and DC motor control must be highly efficient and consume little power, offering longer operation without affecting performance quality. The need to implement smaller, more cost-effective motors in traditional motor applications is also influencing electronic motor control techniques for the industrial sectors.

Expensive computer and power electronics have been significant obstacles to overcome for motor control applications. Integration that combines , flash memory, and FPGA fabric in a monolithic device is helping designers face these challenges. For the first time, engineers can combine the motor control analog front end, high-speed flash lookup tables, and deterministic algorithm processing capabilities of programmable logic into a single-chip solution.

Tradeoffs? What tradeoffs?

Low-power solutions are the biggest growth segment for electronics design, but until recently that design imperative often came at the cost of designing out performance or functionality or missing out on integration opportunities.

Increasingly, however, those traditional tradeoffs are not so onerous. FPGA vendors have integrated microcontroller and microprocessor cores into their devices. Some of these approaches feature very low operating current and static power, consuming only 24 µA in static mode and 3 µA in sleep mode. The Flash Freeze mode that Actel employs, which enables easy entry and exit from ultra-low power modes while retaining SRAM and register data, reduces quiescent current to 20 µA. The feature also allows instant on/off cycling of the processor core for maximum performance and minimum power consumption.

This is approximately 200 times less static power than competitive FPGA offerings and delivers more than 10 times the battery life of the leading programmable logic devices in portable applications.

There’s a similar advantage where analog meets digital. FPGAs integrate programmable logic, RAM, flash, and analog onto a single chip, while lowering overall system power. A flash-based approach to mixed-signal FPGAs does not require additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability. Increased functionality can remove several additional components from the board, such as flash memory, discrete analog ICs, clock sources, EEPROM, and real-time clocks, thereby reducing system cost and board space requirements.

Conclusion

Today, FPGA technology is increasingly used in low-power applications. FPGAs have been adopted widely in recent years due to advanced technology that lowered the unit price, but the price reductions have come with higher power consumption due to higher transistor leakage.

In addition, smaller cores, better IP and development environments, and the double-time march of technology has created a situation in which processor and controller cores and mixed-signal functionality can now be part and parcel of FPGAs. This integration provides a single-chip solution that lowers overall power, cuts costs, and reduces design complexity. It also broadens a designer’s application reach and time to market.

FPGAs are bringing to market low-power features at exactly the moment when power conservation and design flexibility are most required to meet evolving customer demand.

Christian Plante is Director of Marketing low-power and mixed-signal FPGAs. Christian joined Actel in 2008, bringing with him more than 14 years of experience in the semiconductor and computer hardware industries. Prior to joining Actel, he was the Director of Customer Marketing at Cswitch Corporation and also held several senior marketing positions at Altera Corporation. He holds a Bachelor's of Science degree in electrical engineering from Laval, Quebec City, Canada and a Master’s degree in business administration from Queen's University, Kingston, Canada.


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