Tipping points in programmable logic: Is FPGA design more complex than ASIC design?
Assessing which ASIC tool technologies will prove useful to FPGA tool flows
The ASIC world has many degrees of freedom; the FPGA world, not so much. But as Andrew Dauman, who will be presenting the keynote address at the first annual FPGA Summit, points out, far fewer than six degrees of separation may keep the two apart.
In the 25-year history of programmable logic, every year has seen major business upheavals set off both by the application of Moore's law to the devices and by necessary design methodology adaptations. At the leading edge of FPGA design, the techniques and expertise employed are every bit as challenging and sophisticated as those used in ASIC design. In ASIC design, the leading-edge CMOS geometries are used to create very large scale systems on a chip. The parasitic and secondary effects of employing CMOS geometries at 90nm and far below have led to front-end ASIC tools (and designers) having to be more and more engaged in the back-end procedures. For example, most ASIC designers demand the use of Physical Synthesis at the front end in order to drive timing closure at the back end. Front-end ASIC designers are given additional burdens of Design-for-Manufacturing, Design-for-Test, Design-for-Reuse (IP), Design-for-Low Power, and the like, all of which are complex and interdependent.
In the ASIC world, there are many degrees of freedom in the end silicon, and the previously mentioned burdens of the modern ASIC designer are all examples of the responsibility that comes with that freedom. The Electronic Design Automation (EDA) industry has done a sterling job in providing tools that allow these burdens to be borne and for ASICs to be produced at 40nm and soon beyond – an astounding achievement that seemed impossible only a few years ago.
FPGA designers, on the other hand, do not have such freedoms; this is both their blessing and their curse.
FPGA vendors make enormous investments in creating a new FPGA family. They are performing the very tasks mentioned above and they are doing it not only for a single design, but to produce a device that addresses a very wide range of applications. In effect, they are carrying the burden of 40nm design for their end users.
How FPGA designers manage hurdles
Compared to ASIC designers, FPGA designers lack freedom. We are limited to exactly the resources, timing, routing, power and other parameters that are encapsulated into the FPGA silicon. This places extreme constraints on FPGA tools and designer efficiency. An ASIC design team can place fine-grain cells, create extra routes as required, or move resources while considering the multi-axis trade-offs involved. In the FPGA realm, however, cells are fixed and coarse-grained. What's more, routing is finite with quantized delays, so if we require an extra route where none is available, then the effects often ripple widely throughout the design.
The predefined coarse-grained nature of FPGA architectures would be an extremely difficult hurdle for today's ASIC design teams if they were faced with such fundamental constraints, so how do FPGA designers manage?
Traditionally, FPGA designers are not expecting a detailed level of involvement in their designs; and this must not change. They work at an abstracted level from the silicon and depend upon their tools to make the trade-offs mentioned earlier quickly, automatically, and without error. At Synopsys, we have devoted more than 14 years of R&D effort to developing the methodology and tools that maintain this abstraction, even at the very leading edge of FPGA technology. For example, by modeling all routing resources, their timing, their sources, and their blocking inter-dependencies, we created a Physical Synthesis solution that combines Synthesis with Place and Route. Revisiting our earlier example, routes may be ripped up and rerouted elsewhere to make room; on the other hand, physical synthesis might more subtly employ local resynthesis in situ, thus altering the placement or even the actual logic functions to be placed and alleviating the original routing bottleneck. In effect, we combine the back end and front end in a single-pass automated methodology.
As the R&D groups within the Synplicity Business Group join those of Synopsys, we have new access to many and varied ASIC tool technologies. Many of these are not applicable to FPGA, but some may prove to be of crucial benefit to FPGA tool flows of the future. Beyond the delineated worlds of FPGA or ASIC, an additional wider universe of system design waits, including algorithmic modeling, embedded software, and virtual prototyping. We have already teamed up to face those challenges, too.
The FPGA Summit takes place December 9-11 at the Wyndham Hotel in San Jose, California.