Tool providers focus on improving the efficiency of FPGA design
As the available gate count in FPGAs continues to grow, with 28 nm devices now in full production, more automation is required in design flows to enable engineers to deal with the increased complexity. In a typical FPGA design flow, engineers start implementation with a Register-Transfer Level (RTL) description of the design functions, written (mostly manually) in Hardware Description Languages (HDLs) such as Verilog, VHDL, or System Verilog. The RTL description becomes one of the inputs to logic synthesis, which automates the creation of the actual gate-level circuit structure.
In order to meet performance objectives, designers must also supply the synthesizer with constraints for timing specifications, such as clock rate and delays. Once the gate-level netlist is created, these constraints will guide the place and route tools in the creation of the physical layout. The challenge, for designers, is to be able to create a set of inputs that allow a design to be synthesized and optimized for the architecture of the target FPGA, while also being able to achieve “timing closure.” This is usually an iterative process, and can often be a major source of project delays when closure cannot be quickly achieved.
Speeding design with automation
EDA vendors and FPGA manufacturers are collaborating to improve the design process. At the Design and Verification Conference (DVCon) in February, EDA tool developer Blue Pearl Software announced that they had collaborated with Synopsys to accelerate timing closure in FPGA design by automating the generation of timing constraints directly from the RTL. Blue Pearl has tightly integrated their timing analysis tools with the Synopsys Synplify Pro FPGA synthesis tools, using the pre-synthesis register map as an input for the generation of optimized constraints in the Synopsys Design Constraint (SDC) format. Optimization is a critical part of the constraint-generation process because an over-constrained design is difficult and more time-consuming to synthesize. Blue Pearl has indicated that this technique could potentially be adapted for other synthesis tools as well, such as the Xilinx ISE Design Suite or Altera’s Quartus design software.
Working with new tools
Many DSP-FPGA designers begin developing and testing their architectures using the MathWorks MATLAB simulation tools. The challenge here is mapping the simulation model to an FPGA implementation by converting the MATLAB “.m” language into synthesizable RTL code. To make that job easier, in March MathWorks announced the addition of HDL coder capability to MATLAB, which was previously only available for users of their Simulink model-based design tool. MathWorks designed the HDL coder workflow for direct integration with the Xilinx and Altera synthesis tools, but engineers can also use it for ASIC designs with other EDA tools.
New capabilities in the MATLAB HDL Coder Graphical User Interface (GUI) include the ability to automatically convert floating-point models to a fixed-point design. The HDL coder tool also has the capability to perform optimizations of the finite resources that are available in the target FPGA, and provides iterative reports to guide the process. For designers of high-reliability military/aerospace applications, the MathWorks HDL Coder provides for algorithm-to-HDL traceability to facilitate compliance with the DO-254 guidelines for design assurance of airborne electronic hardware.
To close the loop from synthesis to verification, designers can use MathWorks HDL Verifier (formerly known as EDA Simulator Link) for co-simulation and regression testing of MATLAB with Verilog/VHDL simulators. HDL Verifier also facilitates FPGA-in-the-loop verification, and currently supports a set of 15 FPGA evaluation boards from Altera and Xilinx.
Upgrading to the next level of design
An obvious area calling for more automation is in the synthesis of RTL from higher-level C-language models, commonly referred to as Electronic System Level (ESL) design. More interest in system-level FPGA design can be expected with the introduction of SoC-like devices based on embedded ARM cores by Xilinx and Altera. The design methodology for these devices brings together software engineering for processor-based systems with hardware engineering on the FPGA fabric. While some promising results have been reported for ESL tools from the FPGA and EDA vendors, more improvements are required to achieve great adoption.
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