Two competitive FPGA methodologies for run-time reconfiguration

While a significant amount of time and effort has been dedicated to solving the run-time reconfiguration challenge in FPGAs, the resolution can come from two very different approaches.

Modifying or changing the functional configuration of a device during its operation is a feature unique to FPGAs. For years, FPGA designers have been able to reconfigure a portion of their design with a new bitstream, either through hardware or software. Ryan and David discuss run-time reconfiguration approaches in the FPGA arena.

The ability to perform run-time reconfiguration is primarily used in communications, military, and consumer applications as an approach to reducing component count and power consumption. Examples of run-time reconfiguration applications include Software Defined Radio (SDR), field testing, airborne applications, and remote sensors. While a significant amount of time and effort has been dedicated to solving the run-time reconfiguration challenge in , the resolution came from two very different approaches.

Two approaches to run-time reconfiguration

Currently, there are two FPGA-based solutions to run-time reconfiguration: (PR) employed by Xilinx and Software Programmable Reconfiguration (SPR) used by Altera. The more ambitious PR approach necessitates an designed to support reconfiguration zones. With the SPR approach, FPGA components are created as highly flexible building blocks controlled and manipulated through code running on an embedded processor or even through host software running on a general-purpose processor (GPP).

Partial Reconfiguration

Partial Reconfiguration is a design flow that creates reconfiguration regions in an FPGA. Figure 1 shows the of Xilinx's family of FPGAs that allows design modules to be swapped on the fly using this PR methodology. This capability allows limited resources within the device to be timeshared (reconfigured) while mission-critical or other base design requirements continue to operate in system.

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Figure 1
(Click graphic to zoom by 2.3x)

The FPGA is divided into reconfiguration regions, and a partial bitstream must be created for programming each. The FPGA continues to operate mission-critical functions and meet external interface requirements while reconfiguration regions are reprogrammed to provide different functionality. An analogy can be drawn with a microprocessor methodology known as context switching, which is where the current state is preserved in order to switch to a different process. , however, switches the functional hardware, not a software state. The main advantage of this methodology is that mission-critical operations can be preserved, while only part of the FPGA device is reconfigured, as opposed to full reconfiguration of the FPGA, which does not allow for uninterrupted operation.

FPGAs using PR are typically limited to a single reconfiguration region that falls within logic column boundaries, adding significant additional timing constraints. Although these FPGAs currently promote a design flow offering partial reconfigurability, only available through Application Engineering, there is no robust documented design methodology to guide a user through the implementation of the reconfiguration region. In order to implement PR, a strict design methodology must be followed:

  • Insert bus macros between the PR modules and the static portion of the design
  • Follow the PR synthesis guidelines to generate a partially reconfigurable netlist
  • Create floor plans for all PR and cluster static modules
  • Place bus macros
  • Follow PR-specific design rules
  • Run the PR implementation flow

Due to the strict guidelines, requirements, and a steep learning curve, significant effort is required to implement PR. The required methodology significantly complicates efforts, lowering the abstraction level and forcing developers to focus their time and efforts on device-dependent designs close to the gates. In an effort to achieve more design flexibility and reduce risk, PR adds a significant amount of design risk to programs, especially those in the military sector. In addition, the PR approach is very dependent on tool version and device, limiting the designer's selection of FPGA for size, I/O capability, and power. (Currently, there is no PR support for Spartan-class FPGA devices.)

Software Programmable Reconfiguration

Software Programmable Reconfiguration is the designed-in capability used by Altera to modify digital logic flows through internal or external software commands in the Cyclone family of FPGAs. SPR is a methodology that leverages existing IP and design software to provide an FPGA reconfiguration solution superior to PR. By taking a more software-based approach to FPGA development and looking at the FPGA as a System-on-Chip (SoC) with the peripheral infrastructure in place, the goals of SPR and rapid development of FPGA-based Software Defined Radio applications can be achieved with all of the previously stated advantages. Figure 2 shows the similarities between a SPR implementation and a standard microprocessor with peripheral support.

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Figure 2
(Click graphic to zoom)

The application is separated into two distinct processing planes, each utilizing a common interface standard for component interconnect. The first is the control plane used for control, (re)configuration, status, and memory management. Routing of control/configuration and status is accomplished with a control fabric. The second plane is the streaming data plane. Each of the processing blocks is connected to a streaming data fabric that allows for point-to-point data transfer between waveform components.

The functionality of an FPGA can be increased significantly by using SPR, as the developer is able to raise the abstraction level to one similar to software. Additionally, design and hardware reuse is promoted, which allows multiple waveforms to be implemented on one device or across multiple devices and component building blocks that can be reused with each different application. The integration of a soft-core microprocessor into the design improves design exploration and test, providing a method of control, status, and flexible, real-time adaptive reconfiguration. Instead of redesigning, rewriting HDL, simulating, resynthesizing, and finally, reprogramming the FPGA every time a change is required, the whole range of application requirements are implemented and all the necessary adaptive software reconfigurable components are deployed to a single device or across multiple devices for easy software reconfiguration. As with microprocessors, this type of high level design is scalable, allowing for an increase in application complexity, mapping directly to an ASIC flow, and resulting in a significant increase in overall design portability.

Instead of reconfiguring the device with a new bitstream, the whole application is implemented with a single unchanged bitstream, integrating all components in a single device. A control plane provides a path for control, configuration, and status of the implemented components, allowing dynamic reconfiguration and feedback of each function. It also allows commands to be sent to the streaming data switch fabric, reconfiguring the date path and allowing other functions to operate.

Similar components within each function can be shared by multiple functions to save resources. In addition, a mixed Time Division Multiplexed (TDM) mode can be applied that is not supported by Partial Reconfiguration. PR is function A or function B. The SPR-based methodology is not a true TDM function, in that f(x) can be operating while g(x) also operates, sharing only the resources necessary, as shown in Figure 3.

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Figure 3
(Click graphic to zoom)

In order for SPR to meet Size, Weight, and Power (SWaP) requirements using this methodology, FPGAs must feature low power, providing a significant amount of computational resources. By leveraging low-power, high-density FPGAs, the goals of FPGA reconfiguration can be easily achieved. The core static power curve shown in Figure 4 illustrates a comparison of the significant power savings per logic block available in various FPGAs.

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Figure 4
(Click graphic to zoom by 2.5x)

One drawback to SPR is that it has no significant capability to recover from Single Event Upsets (SEUs) as a properly designed PR scheme could theoretically achieve. Specific FPGAs that have memory-scanning capabilities, however, can prevent the propagation of SEU failures, though such a system may require the device to be reconfigured, interrupting operations. It should again be emphasized that for systems using various different waveforms, SPR holds significant assurance in single-FPGA implementations. As Moore's Law continues to hold true, the advantages of SPR implementations will increase.

Future growth opportunities

Current FPGA capabilities for run-time reconfiguration are maturing to meet the needs of military and communications applications. As the capabilities of devices grow, there will be more demand for flexible reuse of FPGA resources. Advances in this area continue to be made in device configuration and reconfiguration speed, built-in error detection and recovery, and ease of design of the reconfiguration modes. Designers will continue developing sophisticated multifaceted designs that require robust implementations of PR. For this reason, work will continue both in developing the capabilities and ease-of-use of PR, as well as SPR. As is the case with many FPGA capabilities, having the technology available today is not sufficient to compel usage; crossing over a “design usability” barrier is required. SPR has both the design usability and reconfigurable features for today's reconfigurability requirements.

David Rupe is BittWare's FPGA product manager. David has spent the majority of his career in the research field, focusing on porta- bility, reuse, and rapid development of FPGA based systems. Originally spending most of his time architecting and implementing FPGA communications systems on both custom and COTs FPGA platforms, he now leads up the FPGA architecture and development efforts for BittWare's latest Altera-based systems. He holds a BA in Computer Engineering from Rochester Institute of Technology and an MA, also in Computer Engineering, from Northeastern University.

J. Ryan Kenny is the technical marketing manager in Altera's military and aerospace business unit. He is responsible for creating FPGA-based technical solutions for the military data and signal processing market. He joined Altera in March 2007 and has more than 10 years of experience in space and defense electronics in the U.S. Air Force and at Lockheed Martin. He graduated from the U.S. Air Force Academy, and completed an MSEE and MBA from California State University Northridge and Santa Clara University respectively.

BittWare, Inc.
603-226-0404
drupe@bittware.com
www.bittware.com

Altera Corporation
408-544-7276
rkenny@altera.com
www.altera.com