Xilinx stacks its chips against the competition

Thomas Edison’s brilliance wasn’t really inventing new things; it was often improving others’ existing ideas and making them “gotta have” mainstream products. Improving upon others’ ideas also comes into play with Xilinx’s Stacked Silicon Interconnect Technology in high-end Virtex-7 FPGAs. The company is creating 3D “stacked” die devices in what could simply be described as a Multi-Chip Module (MCM). But that description would greatly undersell this unique approach to more than doubling logic density in a single package. Xilinx follows Intel’s lead with the current crop of Core i3/5/7 devices that combine the Northbridge/graphics controller with the CPU in a single MCM. But while Intel didn’t have to solve the problem of ultra-low-latency routing of thousands of high-speed signal lines among separate die, Xilinx did. But the ultra-low-latency routing of thousands of high-speed signal lines among separate die is a problem Intel didn’t have to solve, but Xilinx did.

Using the latest 28 nm 7 Series FPGAs, “stacked” silicon die will provide what Xilinx claims to be an industry-leading density of 2 million logic cells. My research concurs that this is indeed the highest commercially available. Five years of Xilinx research and extensive collaboration with packaging and assembly partners makes this possible, even though one tends to think of this as a “So, what? How hard can that be?” announcement. I assure you, it’s whiz-bang. Here’s why.

According to Semico Research, the programmable market for all types of logic will grow by 47.4 percent in 2010, for all types of logic, and FPGAs are growing at 9.4 percent CAGR 2010 to 2015. High-end FPGAs need either more logic density, high-speed transceivers, or both. Market pull for multi-million-cell FPGAs comes from High Performance Computing (HPC) supercomputer nodes, as well as from wired and wireless infrastructure such as cellular base stations and cloud core routers and servers. Certain high-end data mining and military applications like radar are also stoking demand.

In just cellular alone, double-digit growth in wireless data is driving the market. Smartphones and mobile devices need always-on access to the Internet. Fatter RF and back-haul pipes are cost-prohibitive (just ask AT&T), so base station DSP algorithms and Deep Packet Inspection (DPI) have to more efficiently handle increased bandwidth without infrastructure build-out. According to Xilinx, its high-end Virtex-6 FPGAs are found in over more than 50 percent of cellular base stations, with more planned as beyond-3G Long Term Evolution (LTE) becomes a global reality. So the need for more logic without exponentially more cost is acute. But in ICs, “more” always means denser die, fab shrinks, or revolutionary process enhancements such as silicon on insulator or high K dielectrics with thinner gate oxides. The Xilinx Stacked Silicon Interconnect uses lower-cost existing technology to offer “More than Moore.” [1]

To accomplish more than 2x density, Xilinx starts with existing 28 nm technology and creates smaller FPGA die “slices” that interconnect standard I/Os and SERDES via a chip-to-chip silicon interposer. Depending upon the end Virtex-7 device, there are up to 10,000 ultra-low-latency (1 ns), low-impedance die-to-die connections. And since the interposer is passive, power loss is negligible. Unlike MCMs, slices aren’t stacked vertically;, they’re arranged horizontally in the package – the “stacked” refers to the design of the slices where platform devices are made up of layers of logic, memory, SERDES, routing lines, and so on. Those layers are extended to the die’s edges and either connected either to the package substrate, or the adjacent interposer via microbumps and Through-Silicon Vias (TSVs). (See Figure 1.) The interposer itself uses mature 65 nm technology by TSMC, four conventional metal layers, and similar microbumps. Horizontal slices eliminate the abnormal heat dissipation challenges that occur with traditional stacked MCMs.

Figure 1: Microbumps and Through-Silicon Vias extend layers to the die’s edges. Illustration courtesy Xilinx.
(Click graphic to zoom by 1.8x)

High-yield pioneer

The secret sauce in the Stacked Silicon Interconnect Technology isn’t really any one thing; it’s the combination of everything. Xilinx hired AMD's MCM expert Liam Madden, and turned him loose over a period of five years on the technology and supply chain. TSMC had to pioneer a high- yielding interposer technology – and be convinced first that Xilinx wasn’t going to be the only customer. In fact, TSMC Senior Vice President Dr. Shang-Yi Chiang believes the technology will soon be soon commoditized and offered by many vendors. Xilinx is fine with that, as the company will continue to innovate at the slice level by adding additional Platform logic. (As we go to press, Xilinx is preparing another major announcement for high-end Virtex-7 devices.) As well, IBIDEN created break-through package substrate technology, and Amkor fine-tuned microbump, die separation, and assembly procedures. Last and certainly not least, Xilinx spruced up its ISE tool to accommodate the higher-density 7 Series devices such as the LX2000T with unique routing.

And if all this wasn’t enough, Xilinx has just blown the doors off density-per-dollar. Now Xilinx can use mature (read: cheaper) technology to create next-gen densities. Though the company has “no current plans” to introduce custom System-on-Chip (SoC) Platforms – such as FPGA slice + CPU + Ethernet + graphics – it’s a no-brainer that for high-volume markets, the company could soon be selling ASSPs if the money is there.

Indeed, Xilinx is willing to stack its chips up against competing FPGA companies, any time they’re ready. Besides 2x densities over last year, unheard of application-specific SoCs may be available for a fraction of the cost.

[1] It’s cute, and it’s Xilinx’s line, but it sums up the innovation.