asset intertech
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ASSET InterTech's SourcePoint software debugger now offers insight into complex code execution on AppliedMicro's ARM 64-bit HeliX 2 SoCs
The greater visibility of ASSET(r) InterTech's SourcePoint(tm) software debugger now enables engineers to quickly find the root causes of bugs in complex multithreaded code running on AppliedMicro(r)'s 64-bit ARM(r)-based HeliX(r) 2 family of system-on-a-chip (SoC) devices for the embedded market.
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New eBook shows how data mining shortens validation testing on serdes high-speed I/O buses
A new eBook from ASSET InterTech shows how data mining of validation test results can reduce the time spent on validating serdes high-speed I/O buses and predict the risk of failure for new designs.
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ASSET enhances software debug and hardware validation tools for Intel Broadwell-DE microarchitecture
Engineers designing microserver and other hyperscale workload systems based on the new Intel(r) microarchitecture codenamed Broadwell-DE will be able to quickly debug software and validate high-speed communications interconnects with ASSET(r) InterTech's SourcePoint(tm) and ScanWorks(r) platforms. The first generation of the Intel Xeon(r) Processor D family is based on the microarchitecture previously referred to as Broadwell-DE.
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Free IJTAG workshop shows how to re-use embedded instrument IP, reducing costs in chips and circuit boards
A highly technical half-day workshop on the newly approved IEEE 1687 IJTAG standard for embedded instruments will be held in multiple cities across the U.S., Europe and Asia. The free workshop is being instructed by experts from ASSET(r) InterTech and Mentor Graphics(r), two companies that provided leadership to the IJTAG working group.
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ASSET InterTech receives Frost & Sullivan Best Practices Award for Customer Value Leadership
Global market research and consulting firm Frost & Sullivan has recognized the value that ASSET(r) InterTech's SourcePoint(tm) software debug and trace, and ScanWorks(r) hardware validation and test platforms deliver to users by honoring ASSET with a 2015 Best Practices Award for Customer Value Leadership.
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ASSET InterTech and Mentor Graphics IJTAG interoperability empowers two-way validation flow between chips and boards
Seamless interoperability between ASSET(r) InterTech (www.asset-intertech.com) and Mentor Graphics(r) Tessent(r) products for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard will allow engineers to accurately debug and isolate issues in either a complex system-on-a-chip (SoC) or on the circuit board where the chip has been deployed.
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ASSET and Synopsys collaborate on proof-of-concept demonstrating an IEEE P1687 IJTAG tools flow
ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, announced it has collaborated with Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, on a proof-of-concept case study demonstrating the viability of an IJTAG tools ecosystem. Tools are needed to insert and synthesize IEEE P1687 IJTAG embedded instruments into chips and then access those instruments to operate them for circuit board test purposes.
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ASSET's SourcePoint debug and trace tool accelerates software debug of µC/OS - II code
Greater visibility into operating system resources and multithreaded programs accelerates debug and helps software engineers deliver tighter, more robust and higher quality code. With support for the Micriµm(r) µC/OS-II(r) real-time operating system (RTOS), ASSET(r) InterTech's (www.asset-intertech.com) SourcePoint(tm) debugger gives development engineers multiple views of the execution context at every point in the code.
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New tutorial discusses diagnosing defects and variances on DDR memory buses and high-speed serial IO
Slight variances and defects on circuit boards are more difficult than ever to detect and diagnose. Plus, they can result in system crashes and degrade performance later on because their harmful effects are cumulative. A new tutorial by ASSET InterTech (www.asset-intertech.com) investigates how advanced test and debug tools based on instruments embedded in chips are able to identify the root causes of defects and variances in complex chips and circuit boards.
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ASSET's Arium software debugger turbo charges ARM's System Trace Macrocell
Accelerating the tracking of software bugs through mountains of trace data back to their root causes shortens the development of multicore, multithreaded systems-on-a-chip (SoC) by months and delivers new products to market sooner. Enhancements to ASSET(r) InterTech's Arium hardware-assisted SourcePoint(tm) debugger optimize the processing of ARM's System Trace Macrocell (STM), which provides developers a system-level perspective of trace data.
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ASSET's Arium tools will debug ARMcode in TI's multicore OMAP architecture
Designers of systems based on one or more Texas Instruments (TI) OMAP application processors with ARM cores can now debug software and firmware code faster with ASSET(r) InterTech's Arium SourcePoint(tm) debugger for ARM.
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ASSET ScanWorks demonstrates compatibility with new IJTAG standard for embedded instruments
Full compatibility with the soon-to-be-ratified IEEE P1687 Internal JTAG (IJTAG) standard for ASSET(r) InterTech's ScanWorks(r) platform for embedded instruments will mean that developers and test engineers will have a powerful suite of IJTAG tools to ensure the standard's rapid adoption in the industry. ASSET (www.asset-intertech.com) is the leading supplier of tools for embedded instrumentation.
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ASSET announces new bundle of validation and test tools for Intel Xeon, Core and Atom designs
ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, announced today at the Intel Developers Forum a new bundle of ScanWorks HSIO tools for the Intel Architecture (IA). Previously licensed separately, ScanWorks HSIO for IA now delivers greater value to developers by bundling tools for all three Intel silicon brands, Xeon, Core and Atom, under one license.
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How to do functional tests on I2C and SPI monitors with JTAG is explored in new eBook from ASSET InterTech
A new eBook from ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production.
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New PXI controller for ASSET's ScanWorks platform supports four test technologies
With the new PXI-based controller for ASSET(r) InterTech's ScanWorks(r) platform for debug, validation and test, engineers can test circuit boards with four different toolsets, each based on a different test technology. ASSET (www.asset-intertech.com) is the leading supplier of tools for embedded instrumentation.
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New tutorial explains how IJTAG standard streamlines chip validation and characterization -- IEEE P1687 IJTAG standard simplifies and automates management of embedded on-chip instruments
A new introductory tutorial explains that IEEE Internal JTAG (IJTAG) standard simplifies and automates how chip designers manage embedded instruments validate and characterize chip designs. The IJTAG standard specifies a standard interface to instruments embedded in chips, and defines a methodology for accessing them, automating their operations and analyzing their outputs. To allow for a wide variety of functionality, an instrument's core intellectual property (IP) does not need to conform to the IJTAG standard, just the instrument's interface to the on-chip IJTAG network. Chip designers are better able to manage the instruments that are typically embedded in complex components and systems-on-a-chip (SoC).
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How to test high-speed memory with non-intrusive embedded instruments explained in white paper
A new white paper from ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others.
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New ASSET white paper outlines non-intrusive software tools for fast prototype board bring-up
Bringing up prototype circuit boards is a tipping point in the product development cycle. Unfortunately, it too often becomes a tripping point. Boards that won't come up derail the project, delaying launch and generating staggering opportunity costs. The legacy technologies that have been employed for board bring-up have their limitations. They rely on physically probing the board while probe access is disappearing or expensive fixtures. Now many engineers are turning to software-based non-intrusive embedded instruments to perform tests, to gather validation data and to diagnose any hardware faults that may be present on a circuit board. And these tools can be employed before operating firmware or software have been loaded onto the board.
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