Jerry Ahrens, MTS System Design Engineer, AMD Embedded Solutions
Creating a reliable memory layout is one of the most difficult challenges when laying out a motherboard. It is getting more difficult with each speed enhancement of the DDR3 memory interface. A verified rules-based methodology provides an alternative to time-consuming layout simulation and offers an easy-to-understand method to achieve a reliable solution. Memory layout checking tools, such as those provided by AMD, provide an invaluable resource to verify an in-progress design and the final design. For designers, the bottom line is that while creating a reliable memory interface layout is daunting at best, and challenging at worst, a rules-based methodology coupled with great checking tools can decrease overall effort and time while increasing the quality of the memory-interface layout.