Monique DeVoe, Managing Editor
-
First hardened floating-point DSP blocks in FPGAs increase flexibility, power, and performance
Altera has announced that its Arria 10 and Stratix 10 FPGAs and SoCs are the first IEEE 754-complaint devices with hardened floating-point DSP blocks. The Arria 10 family with hardened floating-point capabilities is available now, with the Stratix 10 family to follow in 2015, along with software tools to assist migration from previous-generation Arria and [...]
-
ARM + DSP makes an optimized SoC
The use of ARM CPUs is growing in Systems-on-Chip (SoC) platforms, as the generic ARM architecture lends well to a wide variety of systems and applications. However, while ARM processors are ideally suited for system management functions, they typically struggle with processing-intensive tasks such as imaging and advanced audio and voice communications. As the need for advanced signal processing continues to increase, application-specific Digital Signal Processors (DSPs) are now being integrated with ARM cores on the die of SoCs to offload demanding data processing from the CPU in order to optimize power consumption and performance.
-
Optimizing performance, power, and area in processors to meet increasing demands
Mobile device, set-top box, base station, and server-class processors all need to increase performance, reduce power draw, reduce turnaround time, and reduce area to keep costs down. Previously, to optimize on-chip IP cores, SoC designers needed indivi...
