Rob Hoyecki, Curtiss-Wright Controls Embedded Computing
-
Boosting embedded DSP processing with open-source-based HPEC supercomputer performance
COTS-based HPEC processing in compact, rugged deployable subsystems promises to deliver supercomputing performance in SWaP-constrained and compute-intensive embedded military applications.
-
SRIO reaches a crossroads in Intel-based DSP designs
PCIe-to-SRIO bridges leverage Intel processors for faster, smaller, and lower power DSP designs.
-
Modular Open Systems Approach: A philosophy whose time has come?
Why are radar and image processing systems buying into the layered architecture the Open System Interconnection (OSI) Reference Model describes?
-
Getting higher resolution analog signals into the digital domain
Why conventional CPU configurations cannot reach the level of processing performance and potential I/O bandwidth the latest FPGA iterations can.
-
Message in a bottleneck: Time to double fabric bandwidth with Gen2 Serial RapidIO
Amid ongoing encouragement to implement open standards, reiterating the value of a common denominator fabric.
-
New 28nm FPGAs deliver greater performance and new challenges to mil system integrators
Tighter timing constraints are among the challenges to anticipate as 28nm becomes ready for prime time.
-
Rugged FPGA I/O team likely to draft XMC/FMC
Real estate broker? How FMCs free up real estate for more I/O.
-
OpenVPX systems speed the move to all-digital RADAR
It's a match: An architecture that's scalable (OpenVPX) takes on the systolic-to-fully-parallel digital beamformer scaling challenge military system integrators face.
-
Latest ADCs will cut IF sampling down to nanoseconds
Why receiver systems are poised for noticeable upticks in range, sensitivity, and selectivity.
-
For floating-point processing, new choice arrives with the new decade
Rob outlines several reasons developers addressing COTS military signal processing have reason to consider the Intel Core i7 micro-architecture.
-
OpenVPX and high-speed interconnects usher in a new era of highly scalable DSP systems
Hinderances to building large-scale DSP systems are falling by the wayside.
-
Why 3U VPX has an edge over CompactPCI for FPGA/DSP military applications
Making the case for a form factor that the mil-aero COTS community can rely on for high-speed fabric support
-
Advanced power management: The next step in DSP board design
Filling an information gap when it comes to power use
-
Developers throttle the bottleneck to grab maximum I/O bandwidth using FMCs
The full potential of FPGAs to process data does not have to be hamstrung by data bottlenecks.
-
Multiprocessor debugging challenges
As multiprocessor systems take on more and more roles as multi-spectral, reconfigurable sensors, successful debugging can shorten the time it takes solutions rooted in these systems to reach warfighters.
-
Single-source approach speeds delivery, mitigates risk for radar and signal processing systems
Radar and sonar systems are hugely complex animals. They don’t just rely on garden-variety single board computers; they need sensor processor front ends, intermediate signal converters, legacy military interfaces, graphics processors, and other functions. Rob Hoyecki cautions that because of the complexities involved, it’s advisable to stick with a single systems integrator to pull all these bits together.
