Thomas L. Anderson, Breker Verification Systems
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Hitting the wall in FPGA SoC verification
The ability to fix bugs by reprogramming has been a huge benefit for FPGA designers. Many have made do with little or no verification, preferring instead to debug the design in the bring-up lab. This method is breaking down in the era of FPGA SoCs with embedded processors. FPGA teams can greatly increase the quality of their verification by adopting a method used by many leading-edge ASIC and custom SoC developers: automatic generation of multithreaded, multiprocessor, self-verifying C test cases.
