Recent Blog Posts
-
FPGA designers turn to machine learning in the cloud
Even with all the attention focused on mobile-device apps for everything from ride sharing and Instagram to music streaming, the semiconductor industry still holds sway for passionate engineers who want to make a difference – even if the application is far removed from the consumer experience. One such example involves a couple of savvy engineers [...]
-
Why modern SoC designs embrace emulation
If there is a single largest factor that has driven the evolution of hardware emulation as a primary verification tool, it is system-on-chip (SoC) design. These designs continue to grow in size and functionality and require more IP and interfaces. Emulation technology also caters to the entire SoC development cycle by testing the hardware properties [...]
-
Biggest security threats for embedded designers
Embedded system designers face a number of threats to the applications that they develop for the Internet of Things (IoT). One of the biggest threats comes from IoT devices that end-users can access, such as commercial networked HVAC systems, wireless base stations, power stations, network gateway systems, and avionics networking. Another example is the connected car, including the [...]
-
In-lab FPGA verification is here to stay
I remotely attended the Verification Futures conference, organized by TVS in the UK (you can find the slides on their web site) where NMI’s Doug Amos presented the results of a survey conducted in 2014 about FPGA usage in the UK and Ireland. One aspect that struck me is that the most commonly used FPGA [...]
-
Agile for hardware development
Agile was a strong theme at recent Verification Futures conference, with a number of speakers discussing how they have introduced continuous integration. In 2012 at IP-SOC, I asked “Are we too hard for agile?” Here, I’ll consider how things have changed in the past two years. First, “agile” is a catch-all to describe a wide [...]
-
FPGAs provide better beamforming performance
As signal processing in radar and wireless communications systems has shifted from analog to digital, great effort has gone into the development of advanced beamforming techniques to enable new applications. The ability to precisely guide beams using digital methods, the most common being fast Fourier transform (FFT), has resulted in significant changes in how radar [...]
-
Encrypting communications
During the Afghanistan conflict, it was widely reported that insurgents were intercepting and displaying the unencrypted video feeds from UAVs using inexpensive software sourced from the web. This shocking revelation suggests that adding an encryption capability is a difficult task, but in reality, it needn’t be. Data encryption is an obvious benefit for UAVs, along [...]
-
Welcome to the Ultra-class zetta FPGA era
It’s time once again for another technology jump. Xilinx just announced tapeout of their new “UltraScale ASIC class” ICs. I’m not sure what that means, but it sure sounds fancy. Why not just “superscale”? This year will be an “ultra” year for Xilinx. The tools are said to be ultra fast as well. The design [...]
-
Scalable design style using SystemVerilog for FPGA designers
Given the trends in FPGA devices, many of the previous generation ASICs can easily be accommodated in modern-day FPGAs. Moreover, even the new ASIC design teams are first exploring doing an FPGA prototype and then doing an ASIC. The FPGA community is becoming more vibrant than ever before thanks to all the technology advancements, tools, [...]
-
Where is my $2 FPGA?
Ever since FPGA companies broke the .2 micron barrier we've been led to believe that gates are free, so use them – FPGAs will take over the world. Today FPGA leaders like Altera and Xilinx are leading the path to 28 nm and beyond. You have oceans of gates that are cheaper than ever, but small embedded microcontrollers can still be a quarter the cost. When compared to an Atmel AVR or Microchip dsPIC, even the smallest of the low-cost FPGA have a hard time competing against them in price and functions.
-
More litigation plagues the EDA industry
Add Cadence and Berkeley Design Automation (BDA) to the list of EDA litigants that will be making more lawyers wealthy in Silicon Valley. First, Synopsys filed suit against Mentor Graphics in September last year, in an attempt to clear their path to an acquisition of Emulation and Verification Engineering (EVE), producer of the ZeBu ASIC [...]
-
Cadence Design Systems to acquire DSP IP provider Tensilica
Cadence Design Systems announced today that they intend to acquire Tensilica, a provider of Silicon Intellectual Property (SIP) for Digital Signal Processing (DSP) applications, for approximately $380M. The announcement follows Cadence’s February 7, 2013 announcement that they would acquire Cosmic Circuits, a design house based in India, which provides SIP for analog and mixed-signal applications, [...]
-
Achronix begins shipping first 22nm FinFET FPGAs
Achronix, a startup in Santa Clara, CA that is building “application targeted” FPGAs, has announced that it has begun shipping their first product – the Speedster®22i HD1000. The company is collaborating with Intel, who is manufacturing the Achronix FPGAs in their 22nm, 3-D Tri-Gate (I.e. FinFET) transistor technology, and also has contributed design IP for the Speedster [...]
-
Altera collaborates with ARM for FPGA SoC toolkit integration
Altera has begun shipping sample quantities of their 28nm Cyclone V SoCs, with the first product being the integration of a dual core ARM Cortex A9 and the 110 KLE FPGA fabric, the largest device in the family. Chris Balough, Senior Director of Product Marketing for SoC FPGA Products at Altera, says that the devices offer an [...]
-
Tektronix Certus 2.0 eases debug of ASIC FPGA prototypes
Tektronix, Inc., has introduced version 2.0 of its Certus ASIC prototyping debug solution, building on capability the company acquired with their purchase of Veridae Systems in July, 2011. Certus integrates directly with RTL design flows, so that verification engineers can more easily incorporate embedded instruments to increase their visibility of ASIC prototype behavior. Brad Quinton, Chief [...]
-
Microsemi announces SmartFusion2 FPGA SoCs
Microsemi has announced the next-generation of their FPGA SoCs, the SmartFusion2 family, which combine a flash-based FPGA fabric with a 166 MHz ARM Cortex-M3 processor on a single chip. The SmartFusion2 will be available in configurations from 5K 4-input Look-Up Tables (LUT) to 120K LUT. The Microprocessor Sub-System (MSS) in the SmartFusion2 consists of a 166 MHz ARM Cortex-M3 [...]
-
FPGAs speed trading on Wall Street
The degree to which financial markets are now run by computers, for better or worse, was brought into the news headlines recently when Nasdaq OMX Group Inc. – the owners of the NASDAQ stock exchange – proposed to pay US$62 million to brokers as compensation for losses attributed to trading “glitches” during Facebook’s now infamous [...]
-
Xilinx CTO makes case for the value of programmability in SEMICON West keynote
At the SEMICON West tradeshow in San Francisco this week, Ivo Bolsens, Senior Vice President & Chief Technology Officer at Xilinx, delivered a keynote address titled ”All Programmable – from Silicon to System“. In his presentation to this semiconductor manufacturing industry audience, Dr. Bolsens made his case for how a fabless company such as Xilinx can work [...]
-
New entrants target the need for custom DSPs in wireless applications
The demand for various forms of wireless connectivity continues to explode, driving more complex requirements for flexible, high-performance, yet low-power DSP in multi-mode baseband processors. In designing a DSP for wireless applications, engineers are challenged to support an increasing number of air interfaces and protocols, from multiple 3G and 4G configurations to new modes of [...]
-
Xilinx introduces new Targeted Design Platforms at NAB show
Xilinx and Tokyo Electron Device Ltd. have developed a new Display TDP for 4K2K Display applications Xilinx has launched a new set of Targeted Design Platforms (TDP), at the 2102 National Association of Broadcasters (NAB) show in Las Vegas this week. The Display TDP supports development of content for emerging quad High Definition 4K2K (Quad [...]
Kirvy Teo, Pulnify
Jean-Marie Brunet, Marketing Director (Emulation Division), Mentor Graphics
Ted Marena, Microsemi Corp.
Frederic Leens, Byte Paradigm
Mike Bartley, Test and Verification Solutions (TVS)
Paul Dillien, Algotronix Ltd.
Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt. Ltd.
Mike Demler, Editorial Director
Mike Demler, Editorial Director
Mike Demler, Editorial Director
Mike Demler, Editorial Director- 1
- 2
