(CHAIS)ing the dream: 100 Gigasamples per second for Analog to Digital Converters

Reality doesn’t byte. The real world is , so converting signals into the digital realm is really important. thinks so, too. The company’s new CHArge-mode Interleaved Sampler technology (CHAIS) achieves sampling rates up to 100 GSa/s for analog-to-digital converters (ADCs). This takes place in plain old CMOS instead of high-power SiGe. Moreover, multiple ADCs with tens of millions of gates of logic and memory can now be combined on a single chip, avoiding the multichip modules of other devices.

Targeting the company’s 65 nm CMOS process, power consumption for a typical is 2 W per channel at 56 GSps, which the company says is “unheard of.” A half-speed mode boasts 28 GSps at 1 W per channel. Internal sampling clocks in at under 100 fs total root mean square jitter and under 500 fs I/Q ADC skew. When combined on-chip with other logic, an ASSP can exceed 50 million gates, so that super high-end communications rates such as fiber optic 100 G Ethernet and OTU-4 can now be realized. The company’s first production device is the DP-DQPSK coherent receiver for 100G optical networks with 4 channels of 56 GSps 8-bit ADCs, logic, and memory all on a single-chip PHY device. Of course, with all this on-chip capability, it’s no longer necessary to move terabits of data between an ADC front-end and an IF processor.