Get a jump start on software development for ARM-based SoC FPGAs
Altera has announced development of a family of ARM-based SoC FPGAs, which will provide users with single-chip solutions that integrate an industrial-grade dual-core 800 MHz ARM Cortex-A9 processor with Altera’s 28 nm low-power Cyclone V and Arria V FPGAs. Each core in the Altera SoC...
Altera has announced development of a family of ARM-based SoC FPGAs, which will provide users with single-chip solutions that integrate an industrial-grade dual-core 800 MHz ARM Cortex-A9 processor with Altera’s 28 nm low-power Cyclone V and Arria V FPGAs. Each core in the Altera SoC FPGA processor system includes a ARM NEON media processing engine and a single/double- precision floating point unit with 32 KB/32 KB (instruction/data) of L1 cache per core. The pair of processors shares an Error Correcting Code (ECC) protected 512 KB L2 cache. Additional hard IP in the SoC FPGAs will include up to three multiport memory controllers with ECC for DDR2/3, Mobile DDR, and LPDDR2 memories. For flash memories, the SoC FPGAs include a Queued Serial Peripheral Interface (QSPI) for NOR and a NAND controller, both with ECC. The SoC FPGAs also provide up to two PCIe Gen 2 x4 interfaces as hard IP and soft IP is available for users who require PCIe x8 configurations.
Altera has also partnered with EDA vendor Synopsys on the development of a new virtual prototyping system for the SoC FPGAs, which the company has dubbed a Virtual Target. Hardware designers will also be able to use Altera’s Quartus II design software, and the Qsys system integration tool. Software designers will be able to perform immediate device-specific embedded software development for the processor system in the SoC FPGA devices prior to availability of silicon. According to Altera, the Virtual Target is a binary- and register-compatible, functional equivalent of an SoC FPGA board, which will enable users to transfer software developed on the Virtual Target to the actual board with minimal effort when it is available. Altera is supporting Linux and the Wind River VxWorks RTOSs in the Virtual Target, and software engineers can also continue to employ the ecosystem of ARM development tools. The Virtual Target includes the same processor and system peripherals that will be in the Cyclone V and Arria V SoC FPGAs, along with real board-level I/O connectivity to a host PC, including DDR SDRAM, Ethernet, USB, and flash memory. Altera is also planning to offer an optional FPGA-in-the-loop extension to the Virtual Target, which will enable users to connect an Altera FPGA development board to the PC-based Virtual Target over a PCIe interface for development of customer-designed FPGA-based IP.