Two million logic cells is the new FPGA standard

The Xilinx Virtex-7 2000T heralds the next era of Moore’s Law, in which 3D stacking of ICs will take over for two-dimensional scaling. The decades-long doubling of device density that has been achieved by shrinking transistors with each new processor generation is approaching limits imposed by semiconductor device physics and the economics of manufacturability. Xilinx is employing a 2.5D technique, in which four 28 nm FPGA die are attached in close proximity on a passive silicon interposer, enabling more than 10,000 high-bandwidth die-to-die interconnections while reducing the power consumed by package-to-package I/O on a printed circuit board by a factor of 100x.

The FPGA integrates a total of more than 6.8 billion transistors for an equivalent logic density of 1,995K logic cells. Xilinx is manufacturing their 7-series devices, which include the Virtex, Kintex, and Arteris families, in TSMC’s 28 nm High Performance Low Power (HPL) high-K metal gate HKMG process. A total of 36 Xilinx GTX transceivers are available in the 2000T, with a peak transceiver speed of 12.5 Gbps. DSP performance, for an example symmetric filter, is specified by Xilinx at 2,756 billion multiply-accumulate operations per second (GMACS). The Virtex-7 2000T contains 46.5 Mb of block random-access memory (BRAM). The 1,200-pin package includes a Gen2x8 PCI Express (PCIe) interface. Xilinx has announced that engineering samples are shipping now.