Scalable design style using SystemVerilog for FPGA designers
Given the trends in FPGA devices, many of the previous generation ASICs can easily be accommodated in modern-day FPGAs. Moreover, even the new ASIC design teams are first exploring doing an FPGA prototype and then doing an ASIC. The FPGA community is becoming more vibrant than ever before thanks to all the technology advancements, tools, and methodologies surrounding the same.
Traditionally, FPGA designers have been using VHDL and Verilog for RTL design quite successfully. VHDL for RTL design is a better choice over Verilog (plain Verilog including 2001 standard) for various powerful RTL design constructs such as Multi-Dimensional Arrays (MDAs), enumerated types, records, etc. With the advent of the SystemVerilog (IEEE 1800-2005) standard, however, things started changing as it incorporated many of the advanced design constructs into the language, bringing cheers to the Verilog preferred FPGA design team. With recent standard updates, the latest SystemVerilog IEEE 1800-2012 has fully incorporated the erstwhile Verilog (IEEE 1364) into the new standard.
Another important aspect for the design community is the tool support for these modern constructs and the good news is most of the FPGA synthesis tools now support SystemVerilog for the RTL Design part fairly well.
To appreciate the positive impact of SystemVerilog for RTL modeling of a scalable design, consider a multi-port networking block as in Figure 1. The device support configurable number of ports on the ingress and egress side.
Figure 1: Sample block diagram of a multi-port networking block.
To keep the design scalable for N number of ports, the array dimensions and bounds need to be parameterized. While Verilog 2001 supports MDAs, it doesn’t allow them in port list. Hence one needs to flatten the array into a single dimension and slice it inside the module. A sample code snippet is shown in Figure 2.
Figure 2: Sample Verilog 2001 code snippet for the multi-port device.
While the port list looks not so difficult, the internal logic to slice the data bus per port is a bit involved. A working code using Verilog’s slicing operators is shown in Figure 3.
Figure 3: Sample Verilog 2001 code snippet for slicing.
And another sample piece of glue logic to detect some header fields using indexed part-select syntax is shown in Figure 4.
Figure 4: Sample Verilog 2001 code snippet using indexed part select.
Sure, none of the above is rocket science, plain mathematics calculating the bounds/indices, but certainly error prone code, specifically around the edges/boundaries. So how does SystemVerilog help? Well, first of all, realize SV is Verilog-and-above, so whatever has been good about previous code will still apply. In this specific example, the enhancement done to the port list to allow MDAs will surely simplify lot of coding. For instance with SV one can model the port list as in Figure 5.
Figure 5: Sample SystemVerilog code using MDAs in port-list.
A quick comparison of Figure 5 and Figure 2 will show the modularity that SV can bring into a scalable design. Now continuing the SV code to the slicing logic, a counterpart of Figure 4, which used index part-select, can now be greatly simplified as the designer can now think “one-port-at-a-time,” avoiding mathematical computes on the indices, etc. Figure 6 shows the same logic as in Figure 4, but with the SV-assisted MDAs.
Figure 6: Sample SystemVerilog code using MDAs.
A quick synthesis with Synopsys’s Synplify Premier 2012.09-SP1 release was performed on this design (Figure 7). For comparison we did both Verilog and SV code synthesis and not so surprisingly, the quality of results remains unchanged across these two representations. Hence FPGA designers can now benefit from the added SV constructs maintaining the same, high Quality of Results (QoR) or at times even doing better with SV and FPGA tools.
Figure 7: Sample RTL schematic with SystemVerilog on Synplify premier.
SystemVerilog has lot more interesting features that can benefit FPGA designers. For more information, see “Upgrading to SystemVerilog for FPGA Designs,” a detailed paper presented at FPGA Camp 2010 at Bangalore, India: http://goo.gl/qoNImw. And read more from CVC Pvt. Ltd. at http://cvcblr.com.
Srinivasan Venkataramanan is Chief Technology Officer, CVC Pvt. Ltd.