Welcome to the Ultra-class zetta FPGA era

It’s time once again for another technology jump. Xilinx just announced tapeout of their new “UltraScale ASIC class” ICs. I’m not sure what that means, but it sure sounds fancy. Why not just “superscale”? This year will be an “ultra” year for Xilinx. The tools are said to be ultra fast as well. The design methodology is ultra fast. I’m wondering, are the parts going to be ultra expensive? I suppose they are happy to finally have something that is similar to an ASIC and have ASIC-strength design methods. Kind of makes me wonder what we have been using before. But does Xilinx’s catch line – “all programmable” – still hold?

The UltraScale marketing started back more or less in December of 2013. Hype about this new ultra-ASIC class of IC started a full two months before the first tapeout of the first IC.

Altera’s not much better. In December of last year they announced Generation 10. Altera will be delivering the unimaginable this year. I suppose if you can’t imagine what is in there, you probably need it. Altera finally did up their processor offerings. The G10 version of the Stratix will have a 64-bit quad core ARM cortex. They are also partnering with Intel to use their 14 nm process. Altera is calling their FET design a “tri-gate” design and Xilinx is calling their FETs “FinFETs.” Xilinx is working with TSMC now. They’ll come out with an initial offering at 20 nm FINFET designs. then die shrink – I mean “turbo charge it” to 16 nm. I’m not sure what comes after UltraScale, but it should be UltraSuperFast devices at 16 nm.

The tri-gate/FinFET designs do solve some real-world issues, mainly leakage currents and power usage. The design is essentially a 3D gate design with oxide on three sides of the gate.

When Altera started their announcements back in December there was only a splash page on their website. Nothing else. You could not find any information about the device or what was in it. No data sheets or applications notes. No white papers. I’m not sure if they were just trying to keep in step with Xilinx or if they really had a product. At least now there is more information that is accessible on their website. Altera is going after zettabyte speeds or zettabyte data transfers or… something relating to zettabyte. To put this in perspective, a zettabyte is 10^21 bytes or 1 billion terabytes. Granted, the I/O capability of the G10 device’s high-speed serial transceivers supports 56 Gigabits per second, it is some fraction of a zettabyte.

Needlesss to say, this year will be interesting in the FPGA (oops, I mean ASIC-class device) market space.

Read Altera’s paper, “Meeting the performance and power imperative of the zettabyte era with generation 10″