Application Feature
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MicroTCA.4 continues culture of COTS signal processing at DESY
In this interview with engineers in the Machine Beam Controls Group at DESY, Holger Schlarb and Michael Fenner discuss the data acquisition requirements of the accelerator community, as well as how a tradition of using COTS signal processing solutions continues to improve uptime and maximize performance for some of the most complex machines on Earth.
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Radiation-tolerant FPGAs solve the satellite signal processing bottleneck
Dramatic increases in sensor resolution in remote-sensing space payloads are causing a processing bottleneck, as downlink bandwidth is not keeping pace. Operators require onboard processing so that satellites send processed information, not just raw data. It is a growing challenge for the roughly 100 remote sensing satellites launched each year, each carrying as many as eight payload instruments. Flash-based field-programmable gate array (FPGA) technology is now being applied to the problem, combining high-speed signal processing with special built-in radiation mitigation techniques to keep systems operational in harsh radiation environments.
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Beamforming: FPGAs rise to the challenge
Several design approaches exist for implementing beamforming processing tasks, with options ranging from GPUs to multicore CPUs, DSPs, and FPGAs. The unique strengths of FPGAs make them an increasingly appealing choice for beamforming when compared to their counterparts.
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Small radars enable detection in coastal zones
For force protection in tight areas such as coastlines and coastal zones, military leaders are leveraging small, compact surveillance radar systems. Mark Radford, CEO of Blighter Surveillance Systems, discusses this trend and talks about the technology behind small radars with Senior Editor Sally Cole. Edited excerpts follow
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No such thing as too much signal processing for radar & EW systems
Signal processing fuels radar and electronic warfare systems as each application has an unquenchable thirst for more and more bandwidth and performance that is more often than not met by FPGA-based VPX computing systems.
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Digital meets RF
In the not too distant past, computers and RF were not to be in the same room, let alone the same piece of computing equipment. Then over the years the two became friendlier as microprocessors were used to control radios and eventually led to the creation of soft radios and today’s highly popular smart phone.
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Cost benefits of FPGA and FMC for embedded systems development
The FPGA Mezzanine Card (FMC), as defined by industry standard VITA 57.1, can be used to greatly improve project risk management and bring products to market faster due to its flexibility and performance. FMCs are very effective for system upgrades and technology insertion, and using them makes it easier to incorporate new technologies such as higher resolution A/Ds and D/As as they become available.
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Convergence comes to GPU processing for C4ISR
Today, GPU options have expanded to include Intel’s Core i7 products, whose built-in GPU functionality and AVX math library support continues to grow. On the FPGA front, we’re starting to see devices with built-in ARM cores, while discrete GPU devices are delivering expanded functionality as well.
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Strategies for verifying an FPGA design
The escalating cost, time, and risk associated with custom integrated circuit (IC) fabrication has driven increased field programmable gate array (FPGA) usage across electronics applications. FPGAs are larger, faster, and more power-efficient than ever, and bring a number of capabilities unavailable in custom silicon design, such as field updates, multi-function devices, and simplified prototyping, making them an attractive option.
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MIL-STD-1553 IP cores challenge traditional IC implementation
Forty years since its release, MIL-STD-1553 is evolving from traditional Integrated Circuits (ICs) to Intellectual Property (IP) cores integrated with Field Programmable Gate Arrays (FPGAs). The advantages of IP core implementation include cost reduction, the ability to upgrade and adapt a design over time, a smaller size footprint, and improved sourcing. Designers choosing IP cores must consider validation testing, code size, FPGA support, and compatibility with legacy software.
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Can your PCB handle the speed?
The JESD204B high-speed data converter I/O standard provides for serial interface bit rates of up to 12.5 Gbps. Many system designers are embracing this “upgrade” to the digital interface. Its faster serial interface allows them to use fewer high-speed serial transceivers on their FPGA or ASIC. This reduction in the number of I/O traces enables smaller packages, smaller PCBs, and smaller overall product form factors. However, designing a reliable physical interconnect for data rates exceeding 5 Gbps may involve additional effort. As the speed increases, the transmission distance needs to be accounted for and additional channel modeling may be necessary, possibly involving a 3D field solver to ensure signal integrity.
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FMCs provide versatility and modularity across multiple platforms
The VITA 57 specification defining the FPGA Mezzanine Card (FMC) has been adopted since 2008. Today FMCs are commonly used in architectures from VPX to CompactPCI to MicroTCA and more. The versatility of the mezzanine approach allows a broad swath of acceptance in various applications.
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Market conditions swing in favor of the custom SoC
The system-on-chip (SoC) is now a part of almost all electronic systems. As an integrated circuit (IC) that pulls together microprocessor cores, systems logic, and I/O functions, the SoC enables a wide range of product designs and is driving new markets such as the Internet of Things (IoT) and the cyber-physical systems that now underpin many industrial and automotive applications.
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New tool for FPGA designers mitigates soft errors within synthesis
Implementing synthesis-based mitigation offers a redux in the radiation upsets and soft errors that plague shrinking FPGA geometries.
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New developments in DSP design
Advances in DSP development tools and chips that support both fixed- and floating-point circuitries help forge high-level design flows for FPGAs.
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Virtual or real: Prototyping platform(s) for ARM-based FPGA design
SoC FPGAs offer both hardware and software approaches to platform prototyping, each of which confronts different challenges of the hardware-software codesign process.
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CORBA for FPGAs: Tying together GPPS, DSPs, and FPGAs
There are numerous advantages of using CORBA with FPGA-based systems. CORBA support for partial reconfigurability, in particular, speeds development of embedded systems and promotes code reuse across multiple generations of products, to increase portability of applications.
Brandon Lewis, Technology Editor
John McHale, Editorial Director
