Feature
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Manycore processors can replace FPGAs
Latency and scalability are among the criteria to consider when weighing FPGA versus manycore processor use
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System design needs to rise above ìC-levelî
One approach to catching integration problems and design flaws at an earlier stage
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Compressing ADCs defuses data rate explosion in Data Acquisition Systems
If there were a DAS Olympics, algorithms competing in the "Compression for Medical/Wireless" event would be among the fastest.
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Joint FPGA-DSP grab, squeeze, and send effort sees video compression success
Adding an FPGA to a team that includes a hybrid DSP device with a general-purpose CPU and DSP engine makes for a productive take on interfacing with numerous dissimilar video standards, compressing them to a common standard, and transmitting the result over an Ethernet link.
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Performance, flexibility, and efficiency make the case for market-specific DSPs
4G wireless communications processing and HD video/audio processing are among the challenges market-specific DSPs are gearing up to handle.
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Unraveling debug and design verification snags
Growing FPGA complexity need not equal a corresponding growth in costs or time to market.
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Tackling Linux size, modularity, and GPL issues
Kim outlines options for developers facing proprietary kernels and OSs that can substantially limit future architectural choices, driving up costs and reducing profits.
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Portrait of a power miser: Open-architecture DSP core teams with a number-crunching accelerator for audio apps
Embedded DSP-based solutions are stepping to the plate for a squeeze play. Digital audio processing solutions must fit into less space and consume less power than ever.
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FMC modules deliver high-speed I/O from ADCs to FPGAs
Overcoming the difficulty of designing an FPGA with I/O that suits a variety of applications.
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Power vs. performance: The ultimate DSP design challenge
If a clock tree falls in the forest of synchronous high-speed DSP designs, do any necessary computing functions fall with it? No, argues Doug, who makes the case for axing the clock tree to reduce power consumption by up to 40 percent in a high-performance processor.
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Design techniques for FPGA power optimization
FPGA power optimization brings to mind a particularly challenging game of limbo. Fred explains, however, that new design techniques can help FPGAs slip under even a power consumption limbo stick held at a tiny height.
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Trends in FPGA testing and validation
Making the case for a new approach to FPGA debugging and validation
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The drive to lower power
Adding flash memory components to underlying SRAM FPGA technology has drawbacks not encountered with true nonvolatile FPGAs.
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Eye of the beholder: FPGAs convert CMOS imager output to human-viewable RGB
Paul describes using the Altera Cyclone III FPGA in an application to render a CMOS imager’s output human-viewable.CMOS imager Bayer-pattern pixel data conversion to RGB pixel data can be readily accomplished using today’s low-cost FPGA tec...
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Signs of The Time
In his usual style, Will Strauss dishes up the facts and numbers about cell phone growth and DSP chips as well as reports activity at the last Mobile World Conference.
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Programmable logic: The key to effective interface design
Ideally, OEMs should be able to get exactly the interfaces they need, without the cost and drawbacks of buying a fully-featured DSP.
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Heterogeneous hardware platforms capitalize on DSP/FPGA capabilities
Combining FPGAs and DSPs delivers winning solutions for a wide range of applications.
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Accelerating algorithms in FPGAs, one process at a time
C-to-hardware tools can give software programmers access to FPGAs as computing devices.
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Beyond firmware: Modeling the DSP chip to meet telecom industry challenges
Adopting an MDD approach enables developers to gain the most from the opportunity created by the new 32- and 64-bit DSP chips.
Ken Karnofsky, MathWorks
Mark Littlefield, Kontron
