Altera Demonstrates Systems Design Solutions at RadarCon 2014

Booth #9 in Cincinnati from May 19 to 23

San Jose, Calif., - May 15, 2014 – Altera Corporation (NASDAQ: ALTR) is demonstrating its military radar systems solutions with FPGA-based military radar reference designs at IEEE RadarCon 2014 Booth #9 in Cincinnati from May 19 to 23. In addition, Altera will share more about its latest Arria® 10 FPGAs, the only programmable logic devices in the industry to include hardened floating point IEEE 754 DSP (digital signal processing) blocks, making them ideal for radar systems design.

RadarCon highlights the challenges in radar designs as the industry continues to transition from a world of analog antennas with very limited intelligence and configurability to one of digital antennas that offer a high degree of re-configurability and all of the advantages of DSP for each antenna element. Altera engineers will perform in-hardware demonstrations of radar reference designs available for customers today in Altera standard FPGA development kits and will also show the company’s portfolio of FGPA, SoC, Enpirion power devices, and software tools that support radar system design.

Altera military radar reference designs include:

Space-time adaptive processing (STAP), a signal processing technique to achieve order-of-magnitude sensitivity improvements in target detection

An extended Kalman filter (EKF) algorithm implemented in an SOC FPGA for target tracking, navigation systems, adaptive control, and many other dynamic systems.

Time delay digital beam forming - an algorithm that provides significant advantages compared to analog beam forming including multiple simultaneous beams, instantaneous wide bandwidth and element level configurability

Ultra-wideband channelizer running in a productionBittware6UVPX with a signal generator feeding into a multi-Gsps Analog to Digital Converter (ADC)

Arria 10 FPGAs and SoCs Feature Hardened Floating Point

Altera is the only programmable logic company to integrate hardened IEEE 754-compliant, floating-point operators in an FPGA, delivering unparalleled levels of DSP performance, designer productivity and logic efficiency. The hardened floating point DSP blocks are integrated in Altera’s currently shipping 20 nm Arria® 10 FPGAs and SoCs and also will be integrated into the upcoming 14 nm Stratix® 10 FPGAs and SoCs.

Arria 10 DSP datapaths operate at 400-450 MHz and provide up to 1.5 TeraFLOPS (floating point operations per second) of single-precision floating-point DSP performance, well suited for high-precision signal processing.

Low-Power Solutions for Automotive Radar

Altera also offers a solution leveraging low-cost FPGAs to provide a powerful processing platform for automotive radar. These solutions include multiple antenna FMCW (frequency modulated continuous wave) range and Doppler processing, as well as AoA (angle-of-arrival), CA (cell averaging), and OS-CFAR (ordered statistics constant false alarm rate) processing.

Link to download Altera automotive radar reference design

Related whitepapers for further reading:

Implementing Digital Processing for Automotive Radar Using SoCs

Radar Processing: FPGAs or GPUs?