First hardened floating-point DSP blocks in FPGAs increase flexibility, power, and performance

Altera has announced that its Arria 10 and Stratix 10 FPGAs and SoCs are the first IEEE 754-complaint devices with hardened floating-point DSP blocks. The Arria 10 family with hardened floating-point capabilities is available now, with the Stratix 10 family to follow in 2015, along with software tools to assist migration from previous-generation Arria and Stratix devices launching in the second half of 2014.

“This is going to change how people look at FPGAs,” says Albert Chang, Manager of Software and DSP Product Marketing at Altera.

The hardened floating-point 20 nm Arria 10 FPGAs and SoCs will be able to deliver up to 1.5 TeraFLOPs DSP performance, and the 14 nm Stratix 10 FPGAs and SoCs up to 10 TeraFLOPS DSP performance.

Previous Altera device families provided floating-point capabilities as a soft implementation, where logic and routing necessary for those capabilities created a timing bottleneck and a performance limit of 200-250 MHz. Removing the bottleneck with hardened, built-in floating-point capabilities eliminates the need for the previously required logic and routing and increases performance to 400-450 MHz. The new hardened device families will allow designers to choose fixed or floating-point modes, and will be backward compatible with existing designs.

The soft floating-point implementation also limited resource efficiency as designs would run out of logic before DSP blocks, which is no longer the case and designers can use those previously locked up logic elements to add more features, functionality, and be able to use all available DSP blocks. This method also improves overall power consumption with the elimination of thousands of logic elements switching back and forth, and, essentially, increases density.

Developers can also save more time with hardened floating-point capabilities as floating-point algorithms native to C and MATLAB development no longer need to be converted to fixed-point and verified, or resources don’t need to be spent resolving timing issues. This change will allow for a development time saving of up to 12 months.

Chang said that the need for hardened floating-point capabilities was validated when their soft implementation was in demand across a wide variety of markets. In particular, radar applications require floating-point processing and radar developers were the first to adopt the soft floating-point implementation. The military’s cyber domain applications also require floating-point capabilities for data analytics and other tasks. Additional application areas where hardened floating-point capabilities are in demand are oil and gas seismic calculators, search and analytics in data centers, security applications such as facial recognition, risk analysis and other financial market simulations, high performance research like bioinformatics and quantum chemistry, and manufacturing.

For designers using Altera’s Stratix V family with its soft floating-point implementation who want to migrate to the hardened floating-point models, pin compatibility between Stratix and Arria families allows designs to be migrated to Arria 10 to get acquainted with the Arria family devices, and will be able to migrate to the hard floating-point Arria 10 devices in the second half of 2014, and the hard floating-point Stratix 10 family of devices in 2015 as DSPBuilder tools are updated for seamless migration assistance to the Stratix 10.