verification
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Why modern SoC designs embrace emulation
If there is a single largest factor that has driven the evolution of hardware emulation as a primary verification tool, it is system-on-chip (SoC) design. These designs continue to grow in size and functionality and require more IP and interfaces. Emulation technology also caters to the entire SoC development cycle by testing the hardware properties [...]
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Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification
Announcing a new SoC and ASIC emulation and prototyping hardware platform with Xilinx(r) UltraScale(tm) devices, Aldec is enabling FPGAs to accelerate even the largest verification tasks, while bringing unparalleled capacity to FPGA-based prototypes.
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Strategies for verifying an FPGA design
The escalating cost, time, and risk associated with custom integrated circuit (IC) fabrication has driven increased field programmable gate array (FPGA) usage across electronics applications. FPGAs are larger, faster, and more power-efficient than ever, and bring a number of capabilities unavailable in custom silicon design, such as field updates, multi-function devices, and simplified prototyping, making them an attractive option.
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Functional and performance verification of SoC interconnects
Verifying interconnect Intellectual Property (IP) – the "glue" that holds together the cores and IP blocks in a System-on-Chip (SoC) – has become more complicated with advanced SoCs, which require special interconnect IP to perform the on-chip communication function. As a result, functional and performance verification of these SoC interconnects has taken on a new level of complexity. Tools have been developed to simplify verification while providing design engineers the ability to find and fix interconnect problems much earlier in the design cycle.
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Managing SoC complexity with scenario model verification
Graph-based scenario models assist engineers with project management, thorough verification, and other aspects of complex SoC development.
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Reducing bugs in hardware design with EDA and formal verification technology
Complex SoCs are often behind schedule or require re-spins due to bugs not caught by verification. In order to meet hardware design challenges, and improve quality and efficiency, designers can integrate formal verification technology into the design cycle.
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Sage-DA announces a new tool to verify DRC decks - DRVerify acts like ATPG for DRC, targeting complex new process design rules
Sage-DA announces DRVerify, a new tool to verify design rule check (DRC) decks - the latest product in the iDRM design rule compiler platform.
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Universal Multi-Resource Bus: The Gateway to Your Prototype
This paper provides an in-depth look at Synopsys' new UMRBus (Universal Multi-Resource Bus) interface - the unique communications architecture that provides users of HAPS systems with: a built-in mechanism that allows bi-directional data exchange for more efficient debug; co-simulation for fast system bring-up; accelerated transaction-based verification and a physical connection to virtual prototyping environments through standard SCE-MI interfaces.
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Overcoming LTE PHY Design Challenges Using System-level Design Methodologies
The design and development time for hardware, software and systems is painfully short. A comprehensive design and verification methodology is required to meet the tight development schedule while satisfying or exceeding performance criteria.
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C/C++ for Complex Hardware Design
An increasing number of ASIC and FPGA designs are accelerating algorithms and applications directly in hardware (HW) circuits. These HW accelerator cores have become commonplace and are now a key part of product differentiation and the ability to meet market expectations in performance, cost and reliability.
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The Airborne Software Development Challenge
Qualified tools can cut software development costs, improve a company's responsiveness and ensure high integrity for airborne software subject to DO-178B. Esterel Technologies' safety manager, Jean-Louis Camus, analyzes how the soon to be finalized DO-178C update may leverage benefits of model-based development with qualified tools.
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Address system-on-chip development challenges with enterprise verification management
Dynamic and highly competitive marketplace demands are forcing manufacturers to put increasing pressure on product development teams. This white paper addresses the multidimensional challenges posed by verification management and offers a compelling solution known as enterprise verification management solution (EVMS) based on over a decade of development and in-house experience at IBM.
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Secure Anchor Point
The world today is a very large and complex social network. With identity theft and other electronic crime on the rise, an important part of life, for all of us, is knowing 'who to trust'.
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Unraveling debug and design verification snags
Growing FPGA complexity need not equal a corresponding growth in costs or time to market.
Jean-Marie Brunet, Marketing Director (Emulation Division), Mentor Graphics
Aldec
Sage Design Automation
Staff, CPU Technology, Inc.
