Design flow demonstration shows an LTE "scrambler" block moving from ".m-file" algorithm to VHDL verification.
Video: FPGA Design & Verification using Agilent SystemVue and LTE libraries
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SystemVue provides an instrument-grade algorithmic reference for FDD LTE, TD-LTE, and MIMO Physical Layer designs that follows you as you move from .m-file and C++ to VHDL/Verilog to finished hardware. By continuously-verifying your baseband PHY throughout the design process, you can meet aggressive time-to-market requirements, spend less on NRE, and improve your coverage and interoperability with an independent alogrithm/test-vector reference. Why wait until hardware to test your LTE algorithms? Achieve earlier design maturity & algorithmic pre-compliance using the LTE Baseband Libraries for Agilent SystemVue.